TSX5070FN STMicroelectronics, TSX5070FN Datasheet - Page 7

• Manufacturer Part Number: TSX5070FN
• Manufacturer: STMicroelectronics
• Type: PCMr

Specifications of TSX5070FN

• Number Of Channels: 1
• Gain Control: Programmable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Package Type: PLCC
• Operating Supply Voltage (typ): ±5V
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): ±5.25V
• Operating Supply Voltage (min): ±4.75V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

POWER-DOWN STATE
Following a period of activity in the powered-up
state the power-down state may be re-entered by
writing any of the control instructions into the serial
control port with the "P" bit set to "1" It is recom-
mended that the chip be powered down before writ-
ing any additional instructions. In the power-down
state, all non-essential circuitry is de-activated and
the D
TRI-STATE condition.
The coefficients stored in the Hybrid Balance circuit
and the Gain Control registers, the data in the LDR
and ILR, and all control bits remain unchanged in
the power-down state unless changed by writing
new data via the serial control port, which remains
operational. The outputs of the Interface Latches
also remain active, maintaining the ability to moni-
tor and control a SLIC.
TRANSMIT FILTER AND ENCODER
The Transmit section input, VF
ance summing input which is used as the differenc-
ing point for the internal hybrid balance cancellation
signal. No external components are needed to set
the gain. Following this circuit is a programmable
gain/attenuation amplifier which is controlled by the
contents of the Transmit Gain Register (see Pro-
grammable Functions section). An active prefilter
then precedes the 3rd order high-pass and 5th or-
der low-pass switched capacitor filters. The A/D
converter has a compressing characteristic accord-
ing to the standard CCITT A or 255 coding laws,
which must be selected by a control instruction dur-
ing initialization (see table 1 and 2). A precision on-
chip voltage reference ensures accurate and highly
stable transmission levels. Any offset voltage aris-
ing in the gain-set amplifier, the filters or the com-
parator is cancelled by an internal auto-zero circuit.
Each encode cycle begins immediately following
the assigned Transmit time-slot. The total signal
delay referenced to the start of the time-slot is ap-
proximately 165
plus 125 s (due to encoding delay), which totals
290 s. Data is shifted out on D
the selected time slot on eight rising edges of
BCLK.
DECODER AND RECEIVE FILTER
PCM data is shifted into the Decoder’s Receive
PCM Register via the D
lected time-slot on the 8 falling edges of BCLK. The
Decoder consists of an expanding DAC with either
A or 255 law decoding characteristic, which is se-
lected by the same control instruction used to select
the Encode law during initialization. Following the
Decoder is a 5th order low-pass switched capacitor
filter with integral Sin x/x correction for the 8 kHz
sample and hold. A programmable gain amplifier,
which must be set by writing to the Receive Gain
X
0 and D
X
1 outputs are in the high impedance
s (due to the Transmit Filter)
R
0 or D
R
X
1 pin during the se-
I, is a high imped-
X
0 or D
X
1 during
Register, is included, and finally a Post-Filter/Power
Amplifier capable of driving a 300
V, a 600
at peak overload.
A decode cycle begins immediately after each re-
ceive time-slot, and 10 s later the Decoder DAC
output is updated. The total signal delay is 10 s
plus 120 s (filter delay) plus 62.5 s (1/2 frame)
which gives approximately 190 s.
PCM INTERFACE
The FS
beginning of the 8-bit transmit and receive time-
slots respectively. They may have any duration
from a single cycle of BCLK to one MCLK period
LOW. Two different relationships may be estab-
lished between the frame sync inputs and the actual
time-slots on the PCM busses by setting bit 3 in the
Control Register (see table 2). Non delayed data
mode is similar to long-frame timing on the
ETC5050/60 series of devices : time-slots being
nominally coincident with the rising edge of the ap-
propriate FS input. The alternative is to use De-
layed Data mode which is similar to short-frame
sync timing, in which each FS input must be high
at least a half-cycle of BCLK earlier than the time-
slot.
The Time-Slot Assignment circuit on the device can
only be used with Delayed Data timing. When using
Time-Slot Assignment, the beginning of the first
time-slot in a frame is identified by the appropriate
FS input. The actual transmit and receive time-slots
are then determined by the internal Time-Slot As-
signment counters. Transmit and Receive frames
and time-slots may be skewed from each other by
any number of BCLK cycles.
During each assigned transmit time-slot, the se-
lected D
register on the rising edges of BCLK. TS
TS
1/2 bit times of the time-slot to control the TRI-
STATE Enable of a backplane line driver. Serial
PCM data is shifted into the selected D
during each assigned Receive time slot on the
falling edges of BCLK. D
D
SERIAL CONTROL PORT
Control information and data are written into or
readback from COMBO IIG via the serial control
port consisting of the control clock CCLK ; the serial
data input/output CI/O (or separate input CI, and
output CO on the TS5070 only) ; and the Chip Se-
lect input CS. All control instructions require 2
bytes, as listed in table 1, with the exception of a sin-
gle byte power-up/down command. The byte 1 bits
are used as follows: bit 7 specifies power-up or
power-down; bits 6, 5, 4 and 3 specify the register
address; bit 2 specifies whether the instructions is
read or write; bit 1 specifies a one or two byte in-
R
X
1 are selectable on the TS5070 only.
1 as appropriate) also pulls low for the first 7
X
X
and FS
0/1 output shifts data out from the PCM
load to 3.8 V or 15 k load to
R
frame sync inputs determine the
X
0 or D
TS5070 - TS5071
X
1 and D
load to
R
0/1 input
X
R
4.0 V
0 (or
0 or
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