LM81EVAL National Semiconductor, LM81EVAL Datasheet - Page 9

• Manufacturer Part Number: LM81EVAL
• Manufacturer: National Semiconductor

Specifications of LM81EVAL

• Lead Free Status / RoHS Status: Not Compliant

INT
CI
FAN1–FAN2
SMBCLK
SMBData
RESET
A0/NTEST_OUT
A1
AC Electrical Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: The Absolute maximum input range for :
Note 4: When the input voltage (V
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
Note 6: The human body model is a 100 pF capacitor discharged through a 1.5 k
directly into each pin.
Note 7: See the section titled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount
devices.
Note 8: Parasitics and or ESD protection circuitry are shown in the figure below for the LM81’s pins. The nominal breakdown voltage of the zener D3 is 6.5V. Care
should be taken not to forward bias the parasitic diode, D1, present on pins: A0/NTEST_OUT, A1 and DACOut/NTEST_IN. Doing so by more than 50 mV may corrupt
a temperature or voltage measurement.
An x indicates that the diode exists.
Note 9: Typicals are at T
Note 10: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11: TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.
Note 12: Guaranteed at 3/4 scale
Note 13: Total Monitoring Cycle Time includes temperature conversion, 6 analog input voltage conversions and 2 tachometer readings. Each 9-bit temperature and
8-bit input voltage conversion takes 50 ms typical and 56 ms maximum. Twelve bit temperature conversion takes 400 ms. Fan tachometer readings take 20 ms
typical, at 4400 rpm, and 200 ms maximum.
Note 14: The total fan count is based on 2 pulses per revolution of the fan tachometer output.
Note 15: Timing specifications are tested at the specified logic levels, V
+2.5Vin - −0.3V to (1.4 x V
+3.3Vin - −0.3V to (1.8 x V
Pin Name
D1
J
x
x
= T
+
+
+ 0.42V or 6V, whichever is smaller
+ 0.55V or 6V, whichever is smaller.
A
= 25˚C and represent most likely parametric norm.
D2
IN
x
x
x
x
x
x
±
) at any pin exceeds the power supplies (V
15%.
D3
x
x
x
x
x
x
x
x
D4
D
FIGURE 2. ESD Protection Input Structure
= (T
R1
0
0
0
0
0
0
0
0
J
max−T
R2
(Continued)
A
)/
JA
IL
.
for a falling edge and V
IN
9
<
GND or V
resistor into each pin. The machine model is a 200 pF capacitor discharged
IN
+12Vin
Vccp1, Vccp2
+5Vin
+3.3Vin, +2.5Vin
T_CRIT_A
VID4–VID0
DACOut/NTEST_IN
>
V
IH
+
), the current at that pin should be limited to 5 mA. The 20 mA
Pin Name
for a rising edge.
J
max,
DS100072-5
JA
and the ambient temperature, T
D1
x
x
x
x
D2
x
x
x
x
x
x
x
D3
x
x
x
x
A
D4
. The maximum
x
x
x
www.national.com
R1
R1+R2
0
R1+R2
R1+R2
0
0
0
120k
120k
120k
R2