LM81EVAL National Semiconductor, LM81EVAL Datasheet - Page 3

• Manufacturer Part Number: LM81EVAL
• Manufacturer: National Semiconductor

Specifications of LM81EVAL

• Lead Free Status / RoHS Status: Not Compliant

A0/NTEST_OUT
A1
SMBData
SMBCLK
FAN1-FAN2
CI
T_CRIT_A
V
+3.8V)
+
Block Diagram
Pin Description
(+2.8V to
Name(s)
Pin
Number
Pin
5-6
1
2
3
4
7
8
9
Number
of Pins
1
1
1
1
2
1
1
1
Digital I/0
Digital Input
Digital I/O
Digital Input
Digital Inputs
Digital I/O
Digital Output
POWER
Type
The lowest order programmable bit of the serial bus address. This
pin functions as an output during NAND Tree tests (board-level
connectivity testing). Refer to SECTION 11 on NAND Tree testing.
The highest order programmable bit of the serial bus address.
Serial Bus bidirectional Data. Open-drain output.
Serial Bus Clock.
Schmitt Trigger fan tachometer inputs.
An active high input from an external circuit which latches a
Chassis Intrusion event. This line can go high without any
clamping action regardless of the powered state of the LM81.
There is also an internal open-drain output on this line, controlled
by Bit 6 of the Configuration Register (40h) or Bit 7 CI Clear
Register (46h), to provide a minimum 20 ms reset pulse. See
Section 3.3 and Section 9.0 .
Critical Temperature Alarm active low open-drain output. This pin
can be grounded when not used.
+3.3V V
(electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors.
3
+
power. Bypass with the parallel combination of 10 µF
Description
DS100072-2
www.national.com