SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 256

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

268
Index 44h-47h
The structure of this register depends on the value of bit 20.
If bit 20 = 0, Multiword DMA
Settings for a Fast-PCI clock frequency of 33.3 MHz:
Settings for a Fast-PCI clock frequency of 66.7 MHz:
Note:
If bit 20 = 1, UltraDMA
Settings for a Fast-PCI clock frequency of 33.3 MHz:
Settings for a Fast-PCI clock frequency of 66.7 MHz:
Note:
Index 48h-4Bh
Channel 0 Drive 1 Programmed I/O Control Register. See F2 Index 40h for bit descriptions.
Index 4Ch-4Fh
Channel 0 Drive 1 MDMA/UDMA Control Register. See F2 Index 44h for bit descriptions.
Note:
Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration (Continued)
30:21
19:16
15:12
30:24
23:21
19:16
15:12
11:8
11:8
— Multiword DMA Mode 0 = 00077771h
— Multiword DMA Mode 1 = 00012121h
— Multiword DMA Mode 2 = 00002020h
— Multiword DMA Mode 0 = 000FFFF3h
— Multiword DMA Mode 1 = 00035352h
— Multiword DMA Mode 2 = 00015151h
— UltraDMA Mode 0 = 00921250h
— UltraDMA Mode 1 = 00911140h
— UltraDMA Mode 2 = 00911030h
— UltraDMA Mode 0 = 009436A1h
— UltraDMA Mode 1 = 00933481h
— UltraDMA Mode 2 = 00923261h
Bit
7:4
3:0
7:4
3:0
31
20
31
20
All references to “cycle” in the following bit descriptions are to a Fast-PCI clock cycle.
All references to “cycle” in the following bit descriptions are to a Fast-PCI clock cycle.
The PIO Mode format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved.
Description
PIO Mode Format. This bit sets the PIO mode format for all channels and drives. Bit 31 of Offsets 2Ch, 34h, and 3Ch are R/
W, but have no function so are defined as reserved.
0: Format 0.
1 Format 1.
Reserved. Must be set to 0.
DMA Select. Selects type of DMA operation. 0: Multiword DMA
tKR. IDE_IOR# recovery time (4-bit) (value + 1 cycle).
tDR. IDE_IOR# pulse width (value + 1 cycle).
tKW. IDE_IOW# recovery time (4-bit) (value + 1 cycle).
tDW. IDE_IOW# pulse width (value + 1 cycle).
tM. IDE_CS[1:0]# to IDE_IOR#/IOW# setup; IDE_CS[1:0]# setup to IDE_DACK0#/DACK1#.
PIO Mode Format. This bit sets the PIO mode format for all channels and drives. Bit 31 of Offsets 2Ch, 34h, and 3Ch are R/
W, but have no function so are defined as reserved.
0: Format 0.
1: Format 1.
Reserved. Must be set to 0.
BSIZE. Input buffer threshold.
DMA Select. Selects type of DMA operation. 1: UltraDMA.
tCRC. CRC setup UDMA in IDE_DACK# (value + 1 cycle) (for host terminate CRC setup = tMLI + tSS).
tSS. UDMA out (value + 1 cycle).
tCYC. Data setup and cycle time UDMA out (value + 2 cycles).
tRP. Ready to pause time (value + 1 cycle). Note: tRFS + 1 tRP on next clock.
tACK. IDE_CS[1:0]# setup to IDE_DACK0#/DACK1# (value + 1 cycle).
32580B
Channel 0 Drive 0 DMA Control Register (R/W)
Channel 0 Drive 1 DMA Control Register (R/W)
Channel 0 Drive 1 PIO Register (R/W)
Core Logic Module - IDE Controller Registers - Function 2
AMD Geode™ SC2200 Processor Data Book
Reset Value: 00077771h
Reset Value: 00009172h
Reset Value: 00077771h