SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 250

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

260
Offset 12h-13h
In order for the ACPI events described below to generate an SCI, the SCI_EN bit must also be set (F1BAR1+I/O Offset 0Ch[0] = 1).
The SCIs enabled in this register are globally enabled by setting F1BAR1+I/O Offset 0Ch[0] to 1. The status of the SCIs is reported in
F1BAR1+I/O Offset 10h.
15:12
Bit
2:1
11
10
3
0
9
8
7
6
5
4
Description
GPIO_STS. Indicates if PME was caused by activity on any of the GPIOs (GPIO47-GPIO32 and GPIO15-GPIO0).
0: No.
1: Yes.
Write 1 to clear.
For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[3] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
general description of this register above).
F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME. In addition, the selected GPIO must be
enabled as an input (F0BAR0+I/O Offset 20h and 24h).
Reserved. Reads as 0.
PWR_U_REQ_STS. Indicates if PME was caused by a power-up request event from the SuperI/O module.
0: No.
1: Yes.
Write 1 to clear.
For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[0] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
general description of this register above.)
Reserved.
Reserved.
GPWIO2_EN. Allow GPWIO2 to generate an SCI.
0: Disable.
1: Enable.
A fixed high-to-low or low-to-high transition (debounce period) of 31 µs exists in order for GPWIO2 to be recognized.
The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[6] to force an SMI.
GPWIO1_EN. Allow GPWIO1 to generate an SCI.
0: Disable.
1: Enable.
See F1BAR1+I/O Offset 07h[3] for debounce information.
The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[5] to force an SMI.
GPWIO0_EN. Allow GPWIO0 to generate an SCI.
0: Disable.
1: Enable.
See F1BAR1+I/O Offset 07h[3] for debounce information.
The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[4] to force an SMI.
Reserved. Must be set to 0
USB_EN. Allow USB events to generate a SCI.
0: Disable.
1: Enable.
THRM_EN. Allow THRM# to generate an SCI.
0: Disable.
1: Enable
SMI_EN. Allow SMI events to generate an SCI.
0: Disable.
1: Enable.
Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
32580B
GPE0_EN — General Purpose Event 0 Enable Register (R/W)
Core Logic Module - SMI Status and ACPI Registers - Function 1
AMD Geode™ SC2200 Processor Data Book
Reset Value: 0000h