TDA4856/V6,112 NXP Semiconductors, TDA4856/V6,112 Datasheet - Page 37

• Manufacturer Part Number: TDA4856/V6,112
• Manufacturer: NXP Semiconductors

Specifications of TDA4856/V6,112

• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
2003 Sep 30
I
PC monitors
S
(1) See Fig.19.
2
C-bus autosync deflection controller for
no
8CH
S
S
S
all other register contents are random
all other register contents are random
change/refresh of data?
Soft start sequence (XXXX XX10)
Power-down mode (XXXX XXXX)
no
8CH
Protection mode (XXXX XX00)
8CH
Protection mode (XXXX XX00)
8CH
all register contents are random
A
no acknowledge is given by IC
Standby mode (XXXX XX01)
Fig.18 I
SAD
all registers defined?
registers are pre-set
A
A
A
Operating mode (XXXX XX10)
SOFTST = 0
SOFTST = 0
SOFTST = 0
SOFTST = 1
STDBY = 1
STDBY = 0
STDBY = 0
STDBY = 0
yes
SAD
1AH
1AH
START
A
2
C-bus flow for start-up.
DATA
yes
SOFTST = 1
STDBY = 0
A
A
A
V CC
DATA
00H
02H
A P
8.3 V
A P
A P
A P
SOFTST = 0?
L4
(1)
yes
L1
L2
L3
MGL791
no
37
Start-up procedure
V
V
Setting control bit STDBY = 0:
Setting all registers to defined values:
Setting control bit SOFTST = 1:
IC in full operation:
Soft down sequence:
CC
CC
As long as the supply voltage is too low for correct
operation, the IC will give no acknowledge due to
internal Power-On Reset (POR)
Supply current is 9 mA or less.
Internal POR has ended and the IC is in standby mode
Control bits STDBY and SOFTST are reset to their start
values
All other register contents are random
Pin HUNLOCK is at HIGH-level.
Enables internal power supply
Supply current increases from 9 to 68 mA
When V
the I
Output stages are disabled, except the vertical output
Pin HUNLOCK is at HIGH-level.
Due to the hardware configuration of the IC
(no auto-increment) any register setting needs a
complete 3-byte I
START - IC address - subaddress - data - STOP.
Before enabling the soft start sequence a delay of
minimum 80 ms is necessary to obtain correct function
of the horizontal drive
HDRV duty cycle increases
BDRV duty cycle increases
PLL1 and PLL2 are enabled.
Pin HUNLOCK is at LOW-level when PLL1 is locked
Any change of the register content will result in an
immediate change of the output behaviour
Setting control bit SOFTST = 0 is the only way (except
power-down via pin V
See L4 of Fig.19 for starting the soft down sequence.
< 8.3 V:
> 8.3 V:
2
C-bus
CC
< 8.6 V register SOFTST cannot be set by
2
C-bus data transfer as follows:
CC
) to leave the operating mode.
Product specification
TDA4856