CY7C04312BV-133BGC Cypress Semiconductor Corp, CY7C04312BV-133BGC Datasheet - Page 3

• Manufacturer Part Number: CY7C04312BV-133BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C04312BV-133BGC

• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06027 Rev. *A
applications. A port’s burst counter is loaded with an external
address when the port’s Counter Load pin (CNTLD) is
asserted LOW. When the port’s Counter Increment pin
(CNTINC) is asserted, the address counter will increment on
each subsequent LOW-to- HIGH transition of that port’s clock
signal. This will read/write one word from/into each successive
address location until CNTINC is deasserted. The counter can
address the entire switch array and will loop back to the start.
Counter Reset (CNTRST) is used to reset the burst counter.
A counter-mask register is used to control the counter wrap.
Notes:
2.
3.
4.
Top Level Logic Block Diagram
Port 1 Operation-control Logic Blocks
Port 1 Control Logic Block is detailed on page 4.
Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
Counter functionality applies only to CY7C0430BV (64K × 18) device option. These pins are either GND or NC for CY7C04312BV and CY7C04314BV.
I/O
0P1
- I/O
CNTRST
CNTINC
CNTINT
CNTRD
MKLD
CNTLD
CLK
R/W
A
MKRD
OE
17P1
CLK
UB
LB
CE
CE
0P1
P1
P1
P1
P1
P1
0P1
1P1
–A
P1
P1
INT
P1
P1
P1
P1
P1
P1
15P1
[4]
[4]
[4]
[4]
[4]
[4]
[4]
P1
18
16
Port-1
Control
Logic
Port 1
Counter/
Mask Reg/
Address
Decode
[2]
Port 1
I/O
Port 2 Logic Blocks
The counter and mask register operations are described in
more details in the following sections.
The counter or mask register values can be read back on the
bidirectional address lines by activating MKRD or CNTRD,
respectively.
The new features included for the QuadPort DSE family
include: readback of burst-counter internal address value on
address lines, counter-mask registers to control the counter
wrap-around, readback of mask register value on address
lines, interrupt flags for message passing, BIST, JTAG for
boundary scan, and asynchronous Master Reset.
[3]
Port 1
Port 2
MRST
16K/32K/64K × 18
QuadPort DSE
Array
CLKBIST
TMS
TCK
TDI
Port 4
Port 3
Port 3 Logic Blocks
Controller
Port 4 Logic Blocks
Reset
Logic
JTAG
BIST
CY7C04312BV
CY7C04314BV
CY7C0430BV
[3]
TDO
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