CY7C04312BV-133BGC Cypress Semiconductor Corp, CY7C04312BV-133BGC Datasheet - Page 24

• Manufacturer Part Number: CY7C04312BV-133BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C04312BV-133BGC

• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06027 Rev. *A
Counter-Mask Register
The burst counter has a mask register that controls when and
where the counter wraps. An interrupt flag (CNTINT) is
asserted for one clock cycle when the unmasked portion of the
counter address wraps around from all ones (CNTINC must be
asserted) to all zeros. The example in Figure 2 shows the
counter mask register loaded with a mask value of 003F
Bidirectional
Address Lines
CNTRST = 1
CNTINC = 1
CLK
CNTLD = 1
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max + 1
Address
Register
Max
Address
Register
CNTRD
MKRD
Figure 1. Counter and Mask Register Read Back on Address Lines
[31]
Figure 2. Programmable Counter-Mask Register Operation
MKLD = 1
CNTINT
H
H
H
L
2
2
2
2
15
15
15
15
X
0
X
X
2
2
2
2
14
14
14
14
X
0
X
Readback
X
Register
Blocked Address
Register
Counter/
Address
Register
Mask
X’s
0’s
X’s
X’s
unmasking the first 6 bits with bit “0” as the LSB and bit “15”
as the MSB. The maximum value the mask register can be
loaded with is FFFF. Setting the mask register to this value
allows the counter to access the entire memory space. The
address counter is then loaded with an initial value of XXX8.
The “blocked” addresses (in this case, the 6th address through
2
2
2
2
6
6
6
6
Addr.
Readback
X
0
X
X
2
2
2
2
5
5
5
5
0 0
1 1
0 0
1 1
Counter Address
2
2
2
2
4
4
4
4
2
2
2
2
3
3
3
3
0
1
1
1
2
2
2
2
2
2
2
2
0
1
0
1
2
2
2
2
[57]
1
1
1
1
0
1
0
1
2
2
2
2
0
0
0
0
0
1
0
1
Memory
CY7C04312BV
CY7C04314BV
Array
CY7C0430BV
Mask
Register
bit-0
Address
Counter
bit-0
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