CY7C04312BV-133BGC Cypress Semiconductor Corp, CY7C04312BV-133BGC Datasheet - Page 25

• Manufacturer Part Number: CY7C04312BV-133BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C04312BV-133BGC

• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06027 Rev. *A
the 15th address) are loaded with an address but do not
increment once loaded. The counter address will start at
address XXX8. With CNTINC asserted LOW, the counter will
increment its internal address value till it reaches the mask
register value of 3F and wraps around the memory block to
location XXX0. Therefore, the counter uses the mask-register
to define wrap-around point. The mask register of every port
is loaded when MKLD (mask register load) for that port is
LOW. When MKRD is LOW, the value of the mask register can
be read out on address lines in a manner similar to counter
read back operation (see Table 2 for required conditions).
When the burst counter is loaded with an address higher than
the mask register value, the higher addresses will form the
masked portion of the counter address and are called blocked
addresses. The blocked addresses will not be changed or
affected by the counter increment operation. The only
exception is mask register bit 0. It can be masked to allow the
address counter to increment by two. If the mask register bit 0
is loaded with a logic value of “0,” then address counter bit 0
is masked and can not be changed during counter increment
operation. If the loaded value for address counter bit 0 is “0,”
the counter will increment by two and the address values are
even. If the loaded value for address counter bit 0 is “1,” the
counter will increment by two and the address values are odd.
This operations allows the user to achieve a 36-bit interface
using any two ports, where the counter of one port counts even
addresses and the counter of the other port counts odd
addresses. This even-odd address scheme stores one half of
the 36-bit word in even memory locations, and the other half
in odd memory locations. CNTINT will be asserted when the
unmasked portion of the counter wraps to all zeros. Loading
mask register bit 0 with “1” allows the counter to increment the
address value sequentially.
Table 2 groups the operations of the mask register with the
operations of the address counter. Address counter and mask
register signals are all synchronized to the port's clock CLK.
Master reset (MRST) is the only asynchronous signal listed on
Table 2. Signals are listed based on their priority going from
left column to right column with MRST being the highest. A
LOW on MRST will reset both counter register to all zeros and
mask register to all ones. On the other hand, a LOW on
CNTRST will only clear the address counter register to zeros
and the mask register will remain intact.
There are four operations for the counter and mask register:
1. Load operation: When CNTLD or MKLD is LOW, the ad-
2. Increment: Once the address counter is loaded with an ex-
3. Readback: the internal value of either the burst counter or
dress counter or the mask register is loaded with the ad-
dress value presented at the address lines. This value rang-
es from 0 to FFFF (64K). The mask register load operation
has a higher priority over the address counter load opera-
tion.
ternal address, the counter can internally increment the ad-
dress value by asserting CNTINC LOW. The counter can
address the entire memory array (depend on the value of
the mask register) and loop back to location 0. The incre-
ment operation is second in priority to load operation.
the mask register can be read out on the address lines when
CNTRD or MKRD is LOW. Counter readback has higher
priority over mask register readback. A no-operation delay
cycle is experienced when readback operation is per-
formed. The address will be valid after t
CA2
(for counter
The counter and mask register operations are totally
independent of port chip enables.
IEEE 1149.1 Serial Boundary Scan (JTAG) and
Memory Built-In-Self-Test (MBIST)
The CY7C0430BV incorporates a serial boundary scan test
access port (TAP). This port is fully compatible with IEEE
Standard 1149.1-2001
standard 3.3V I/O logic levels. It is composed of three input
connections and one output connection required by the test
logic defined by the standard. Memory BIST circuitry will also
be controlled through the TAP interface. All MBIST instructions
are compliant to the JTAG standard. An external clock
(CLKBIST) is provided to allow the user to run BIST at speeds
up to 50 MHz. CLKBIST is multiplexed internally with the ports
clocks during BIST operation.
Disabling the JTAG Feature
It is possible to operate the QuadPort DSE device without
using the JTAG feature. To disable the TAP controller, TCK
must be tied LOW (V
and TMS are internally pulled up and may be unconnected.
They may alternately be connected to V
resistor. TDO should be left unconnected. CLKBIST must be
tied LOW to disable the MBIST. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
Test Access Port (TAP)–Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
4. Hold operation: In order to hold the value of the address
Notes:
57. The “X” in this diagram represents the counter upper-bits.
58. Master Reset will reset the JTAG controller.
readback) or t
port's clock rising edge. Address readback operation is in-
dependent of the port's chip enables (CE
dress readback occurs while the port is enabled (chip en-
ables active), the data lines (I/Os) will be three-stated.
counter at certain address, all signals in Table 2 have to be
HIGH. This operation has the least priority. This operation
is useful in many applications where wait states are needed
or when address is available few cycles ahead of data.
CM2
SS
(for mask readback) from the following
[58]
) to prevent clocking of the device. TDI
. The TAP operates using JEDEC
CY7C04312BV
CY7C04314BV
CY7C0430BV
DD
0
through a pull-up
and CE
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1
). If ad-