ICS830S21AMI IDT, Integrated Device Technology Inc, ICS830S21AMI Datasheet - Page 5

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ICS830S21AMI

Manufacturer Part Number
ICS830S21AMI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of ICS830S21AMI

Number Of Outputs
1
Operating Supply Voltage (max)
3.465V
Operating Temp Range
-40C to 85C
Propagation Delay Time
2ns
Operating Supply Voltage (min)
2.375V
Mounting
Surface Mount
Pin Count
8
Operating Supply Voltage (typ)
2.5/3.3V
Package Type
SOIC
Duty Cycle
53%
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Not Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS830S21AMILF
Manufacturer:
ICS
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20 000
Part Number:
ICS830S21AMILFT
Manufacturer:
ICS
Quantity:
20 000
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
ICS830S21I
1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Offset Frequency (Hz)
5
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
This is illustrated above. The device meets the noise floor of what
is shown, but can actually be lower. The phase noise is dependent
on the input source and measurement equipment.
12kHz to 20MHz = 0.11ps (typical)
Additive Phase Jitter @ 350MHz
ICS830S21AMI REV. A MARCH 21, 2008

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