IDT74LVCH16276APA IDT, Integrated Device Technology Inc, IDT74LVCH16276APA Datasheet - Page 3

• Manufacturer Part Number: IDT74LVCH16276APA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74LVCH16276APA

• Lead Free Status / RoHS Status: Not Compliant

PIN DESCRIPTION
NOTE:
1.
FUNCTION TABLES
NOTES:
1. H = HIGH Voltage Level
2. A, B = Output level before the indicated steady-state input conditions were
IDT74LVCH16276A
3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
established.
1Bx
CEA1B
CEA2B
Signal
1B
2B
These pins have “Bus-hold”. All other pins are standard inputs, outputs, or I/Os.
A
CE1B
CE2B
H
X
X
X
X
X
OEA
OEB
L
CLK
SEL
(1:12)
(1:12)
(1:12)
2Bx
H
X
X
X
X
X
L
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
SEL
H
H
H
X
L
L
L
Description
Bidirectional Data Port A. Usually connected to the CPU’s Address/Data bus.
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.
Clock Input.
Clock Enable Input for the A-1B Register. If CEA1B is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW).
Clock Enable Input for the A-2B Register. If CEA2B is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW).
Clock Enable Input for the 1B-A Register. If CE1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW).
Clock Enable Input for the 2B-A Register. If CE2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW).
1B or 2B Part Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising
edge of CLK, SEL enables data transfer from 2B Port to A Port.
Synchronous Output Enable for A Port (Active LOW).
Synchronous Output Enable for 1B Port and 2B Port (Active LOW).
Inputs
CE1B
H
L
L
X
X
X
X
CE2B
(1)
H
X
X
X
L
L
X
OEA
H
L
L
L
L
L
L
CLK
↑
↑
↑
↑
↑
↑
↑
Outputs
A
A
Ax
H
H
L
L
Z
(2)
(2)
3
Ax
H
H
H
L
L
L
X
X
X
CEA1B CEA2B
H
H
H
L
L
L
L
X
X
(1)
Inputs
H
H
H
X
X
L
L
L
L
(1)
(1)
OEB
H
INDUSTRIAL TEMPERATURE RANGE
L
L
L
L
L
L
L
L
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
Active
1Bx
B
B
B
H
H
L
L
Z
(2)
(2)
(2)
Outputs
Active
2Bx
B
B
B
H
H
L
L
Z
(2)
(2)
(2)