SSTUA32866EC/G-T NXP Semiconductors, SSTUA32866EC/G-T Datasheet - Page 6

• Manufacturer Part Number: SSTUA32866EC/G-T
• Manufacturer: NXP Semiconductors

Specifications of SSTUA32866EC/G-T

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SSTUA32866_2
Product data sheet
6.2 Pin description
Table 2.
Symbol
GND
V
VREF
CK
CK
C0
C1
RESET
CSR
DCS
D1 to D25
DODT
DCKE
PAR_IN
Q1 to Q25,
Q2A to Q14A,
Q1B to Q14B
PPO
QCS, QCSA,
QCSB
QODT, QODTA,
QODTB
QCKE, QCKEA,
QCKEB
DD
Pin description
Pin
B3, B4, D3, D4,
F3, F4, H3, H4,
K3, K4, M3, M4,
P3, P4
A4, C3, C4, E3,
E4, G3, G4, J3,
J4, L3, L4, N3,
N4, R3, R4, T4
A3, T3
H1
J1
G6
G5
G2
J2
H2
[1]
[1]
[1]
G1
[1]
A2
[1]
[1]
[1]
Rev. 02 — 26 March 2007
1.8 V DDR2-667 configurable registered buffer with parity
Type
ground input
1.8 V nominal
0.9 V nominal
Differential input
Differential input
LVCMOS inputs
LVCMOS input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
1.8 V CMOS
outputs
1.8 V CMOS
output
1.8 V CMOS
output
1.8 V CMOS
output
1.8 V CMOS
output
Description
ground
power supply voltage
input reference voltage
positive master clock input
negative master clock input
Configuration control inputs; Register A
or Register B and 1 : 1 mode or
1 : 2 mode select.
Asynchronous reset input (active LOW).
Resets registers and disables VREF data
and clock.
Chip select inputs (active LOW). Disables
D1 to D25
inputs are HIGH.
Data input. Clocked in on the crossing of
the rising edge of CK and the falling edge
of CK.
The outputs of this register bit will not be
suspended by the DCS and CSR control.
The outputs of this register bit will not be
suspended by the DCS and CSR control.
Parity input. Arrives one clock cycle after
the corresponding data input.
Data outputs that are suspended by the
DCS and CSR control
Partial parity out. Indicates odd parity of
inputs D1 to D25
Data output that will not be suspended by
the DCS and CSR control.
Data output that will not be suspended by
the DCS and CSR control.
Data output that will not be suspended by
the DCS and CSR control.
[2]
SSTUA32866
outputs switching when both
[2]
.
© NXP B.V. 2007. All rights reserved.
[3]
.
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