SSTUA32866EC/G-T NXP Semiconductors, SSTUA32866EC/G-T Datasheet - Page 20

• Manufacturer Part Number: SSTUA32866EC/G-T
• Manufacturer: NXP Semiconductors

Specifications of SSTUA32866EC/G-T

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SSTUA32866_2
Product data sheet
11.4 Partial parity out load circuit and voltage measurement information
V
All input pulses are supplied by generators having the following characteristics:
PRR
Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
Fig 24. Partial parity out load circuit
Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to clock
DD
= 1.8 V
(1) C
10 MHz; Z
clock inputs
V
t
V
inputs
PLH
T
i(p-p)
L
includes probe and jig capacitance.
= 0.5V
and t
= 600 mV.
0.1 V.
PHL
DD
0
waveform 2
.
= 50 ; input slew rate = 1 V/ns
are the same as t
CK
CK
output
timing
inputs
Rev. 02 — 26 March 2007
output
1.8 V DDR2-667 configurable registered buffer with parity
DUT
t
V
PLH
OUT
PD
ICR
.
V
t
LH
ICR
C
0.15 V
L
= 5 pF
(1)
V
ICR
20 %, unless otherwise specified.
t
V
V
PHL
ICR
T
test point
R
002aaa654
L
002aaa503
= 1 k
SSTUA32866
002aaa375
V
i(p-p)
V
V
V
0 V
OH
OL
V
OH
i(p-p)
© NXP B.V. 2007. All rights reserved.
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