SSTUA32866EC/G-T NXP Semiconductors, SSTUA32866EC/G-T Datasheet - Page 12

• Manufacturer Part Number: SSTUA32866EC/G-T
• Manufacturer: NXP Semiconductors

Specifications of SSTUA32866EC/G-T

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 8.
At recommended operating conditions (see
[1]
[2]
[3]
Table 9.
At recommended operating conditions (see
[1]
[2]
Table 10.
At recommended operating conditions (see
SSTUA32866_2
Product data sheet
Symbol
f
t
t
t
t
t
Symbol
f
t
t
t
t
t
t
t
Symbol
dV/dt_r
dV/dt_f
dV/dt_
clock
W
ACT
INACT
su
h
max
PDM
PD
LH
HL
PDMSS
PHL
PLH
This parameter is not necessarily production tested.
VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of t
HIGH.
VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of t
Includes 350 ps of test-load transmission line delay.
This parameter is not necessarily production tested.
Parameter
clock frequency
pulse width
differential inputs active time
differential inputs inactive time
set-up time
hold time
Parameter
maximum input clock frequency
peak propagation delay
propagation delay
LOW-to-HIGH delay
HIGH-to-LOW delay
simultaneous switching peak
propagation delay
HIGH-to-LOW propagation delay
LOW-to-HIGH propagation delay
Timing requirements
Switching characteristics
Data output edge rates
Parameter
rising edge slew rate
falling edge slew rate
absolute difference between dV/dt_r
and dV/dt_f
Table
Table
Table
Conditions
CK, CK HIGH or LOW
DCS before CK , CK , CSR HIGH; CSR
before CK , CK , DCS HIGH
DCS before CK , CK , CSR LOW
DODT, DCKE and data (Dn) before CK ,
CK
PAR_IN before CK , CK
DCS, DODT, DCKE and data (Dn) after
CK , CK
PAR_IN after CK , CK
6), unless otherwise specified. See
6), unless otherwise specified. See
6), unless otherwise specified. See
Rev. 02 — 26 March 2007
Conditions
from 20 % to 80 %
from 80 % to 20 %
from 20 % or 80 %
to 80 % or 20 %
Conditions
single bit switching; from CK
and CK to Qn
from CK and CK to PPO
from CK and CK to QERR
from CK and CK to QERR
from CK and CK to Qn
from RESET to Qn
from RESET to PPO
from RESET to QERR
1.8 V DDR2-667 configurable registered buffer with parity
INACT(max)
Figure
Section
Section
Min
1
1
-
[1][2]
[1][2]
[1][3]
[1]
2.
after RESET is taken LOW.
Min
450
1.2
0.5
1.2
1
-
-
-
-
11.1.
11.2.
SSTUA32866
Min
-
1
-
-
0.7
0.5
0.5
0.5
0.5
0.5
Typ
-
-
-
ACT(max)
Typ
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2007. All rights reserved.
after RESET is taken
Max
4
4
1
Max
-
1.8
1.8
3
2.4
2.0
3
3
3
Max
450
-
10
15
-
-
-
-
-
-
Unit
V/ns
V/ns
V/ns
12 of 28
Unit
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns