74SSTUB32866BBFG IDT, Integrated Device Technology Inc, 74SSTUB32866BBFG Datasheet

74SSTUB32866BBFG

Manufacturer Part Number

74SSTUB32866BBFG

Description

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.74SSTUB32866BBFG.pdf (20 pages)

Specifications of 74SSTUB32866BBFG

Lead Free Status / RoHS Status

Supplier Unconfirmed

Current page: 1 of 20
Download datasheet (259Kb)

FEATURES:

• 1.8V Operation

• SSTL_18 style clock and data inputs

• Differential CLK input

• Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer

• Control inputs compatible with LVCMOS levels

• Flow-through architecture for optimum PCB design

• Latch-up performance exceeds 100mA

• ESD >2000V per MIL-STD-883, Method 3015; >200V using

• Checks parity on data inputs

• Maximum operating frequency: 410MHz

• Optimized for DDR2 - 400 / 533 / 667 / 800 (PC2 - 3200 / 4300 /

• JEDEC R/C E, F, G, H, and J

• Available in 96-pin LFBGA package

APPLICATIONS:

• Along with CSPUA877 DDR2 PLL, provides complete solution for

DESCRIPTION:

1.7V to 1.9V V

per DIMM is requred to drive nine SDRAM loads. In the 1:2 pinout

configuration, two devices per DIMM are required to drive eighteen

SDRAM loads. All inputs are SSTL_18, except reset (RESET) and control

(Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits

optimized for unterminated DIMM loads, and meet SSTL_18 specifications,

except the open-drain error (QERR) output.

Data are registered at the crossing of CLK going high and CLK going low.

Parity is checked on the parity bit (PAR_IN) input which arrives one cycle

after the input data to which it applies. The QERR output is open drain.

configuration, the partial-parity-out (PPO) and QERR signals are produced

two clock cycles after the corresponding data output.

COMMERCIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74SSTUB32866B

1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY

5300 / 6400)

DDR2 DIMMs

This 25-bit 1:1 / 14-bit 1:2 configurable registered buffer is designed for

The SSTUB32866B operates from a differential clock (CLK and CLK).

When used as a single device, the C0 and C1 inputs are tied low. In this

machine model (C = 200pF, R = 0)

2005 Integrated Device Technology, Inc.

operation. In the 1:1 pinout configuration, only one device

1.8V CONFIGURABLE

BUFFER WITH PARITY

C0 input of the second register is tied high. The C1 input of both registers

are tied high. The QERR output of the first SSTUB32866B is left floating and

the valid error information is latched on the QERR output of the second

SSTUB32866B.

for two clock cycles or until RESET is driven low. The DIMM-dependent

signals (DODT, DCKE, DCS, and CSR) are not included in the parity check.

The C1 input controls the pinout configurationfrom 25-bit 1:1 (when low) to

14-bit 1:2 (when high). C0 and C1 should not be switched during normal

operation. They should be hard-wired to a valid low or high level to

configure the register in the desired mode. In the 25-bit 1:1 pinout

configuration, the A6, D6, and H6 terminals are driven low and should not

be used.

the differential input recievers are disabled, and undriven (floating) data,

clock, and reference voltage (V

RESET is low, all registers are reset and all outputs except QERR are forced

low. The LVCMOS RESET and Cn inputs always must be held at a valid

logic high or low level.

connect one of the two V

unused V

system chip select (DCS and CSR) inputs and will gate the Qn and PPO

outputs from changing states when both DCS and CSR inputs are high. If

either DCS or CSR input is low, the Qn and PPO outputs will function

normally. Also, if the internal low power signal (LPS1) is high, the device

will gate the QERR output from changing states. If LPS1 is low, the QERR

output will function normally. The RESET input has priority over the DCS

and CSR control and when driven low will force the Qn and PPO outputs

low, and the QERR output high. If the DCS control functionality is not desired,

then the CSR input can be hard-wired to ground, in which case the setup-

time requirement for DCS would be the same as for the other D data inputs.

To control the low-power mode with DCS only, then the CSR input should

be pulled up to V

supplied, RESET must be held in the low state during power up.

When used in pairs, the C0 input of the first register is tied low and the

If an error occurs and the QERR output is driven low, it stays latched low

The C0 input controls the pinout configuration of the 1:2 pinout from

The device supports low-power standby operation. When RESET is low,

There are two V

The device also supports low-power active operation by monitoring both

To ensure defined outputs from the register before a stable clock has been

REF

pin should be terminated with a V

REF

through a pullup resistor.

pins (A3 and T3). However, it is necessary to only

REF

COMMERCIAL TEMPERATURE RANGE

pins to the external V

REF

IDT74SSTUB32866B

) inputs are allowed. In addition, when

INFORMATION

OCTOBER 2005

REF

coupling capacitor.

REF

ADVANCE

power supply. An

DSC 6892/3

Related parts for 74SSTUB32866BBFG

74SSTUB32866BBFG Summary of contents

Page 1

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY FEATURES: • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer • Control inputs compatible with LVCMOS levels • ...

Page 2

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY FUNCTIONAL BLOCK DIAGRAM (1: CONFIGURATION (POSITIVE LOGIC) RESET CLK CLK V REF DCKE DODT DCS CSR OTHER CHANNELS (D3, D5, D6, D8-D14) COMMERCIAL TEMPERATURE RANGE ...

Page 3

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY FUNCTIONAL BLOCK DIAGRAM (1: CONFIGURATION (POSITIVE LOGIC) RESET CLK CLK V REF DCKE DODT DCS CSR OTHER CHANNELS (D2-D6, D8-D10, D12-D13) COMMERCIAL TEMPERATURE RANGE ...

Page 4

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY PIN CONFIGURATION (TYPE A) 6 Q2B Q3B QCKEB QODTB 5 QCKEA Q2A Q3A QODTA 4 V GND V GND GND V GND DD REF 2 PPO NC NC QERR ...

Page 5

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY FUNCTIONAL BLOCK DIAGRAM (1:1) RESET CLK1 CLK1 V REF DCKE DODT DCS CSR OTHER CHANNELS (D3, D5, D6, D8-D25) COMMERCIAL TEMPERATURE RANGE ...

Page 6

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY PIN CONFIGURATION NC Q15 Q16 QCKE Q3 QODT 4 V GND V GND GND V GND REF DD 2 PPO D15 QERR D16 DCKE D2 ...

Page 7

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY FUNCTION TABLE (EACH FLIP-FLOP) (1) RESET DCS CSR ...

Page 8

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY LOGIC DIAGRAM (1:1) G2 RESET H1 CLK J1 CLK (Internal Node D3 D6 D25 A3 REF PAR_IN G6 C0 Counter R ...

Page 9

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY LOGIC DIAGRAM (1:2) G2 RESET H1 CLK J1 CLK (Internal Node D3 D6 D14 D A3 REF PAR_IN G6 C0 ...

Page 10

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY ABSOLUTE MAXIMUM RATINGS Symbol Description V Supply Voltage Range DD (2,3) V Input Voltage Range I (2,3) V Output Voltage Range O I Input Clamp Current V < > ...

Page 11

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY OPERATING CHARACTERISTICS, T Symbol Parameter V Supply Voltage DD V Reference Voltage REF V Termination Voltage TT V Input Voltage High-Level Input Voltage Low-Level Input Voltage IL ...

Page 12

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE Symbol Parameter f Clock Frequency CLOCK tw Pulse Duration, CLK, CLK HIGH or LOW ACT (1,2) t Differential Inputs Active Time INACT (1,3) t Differential ...

Page 13

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY REGISTER TIMING RESET DCS CSR CLK CLK D1 - D25 Q1 - Q25 PAR_IN PPO QERR Timing Diagram for SSTUB32866B Used as a Single Device ...

Page 14

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY REGISTER TIMING RESET DCS CSR CLK CLK D1 - D14 Q1 - Q14 PAR_IN PPO QERR (not used) Timing Diagram for the First SSTUB32866B (1:2 Register-A Configuration) Device Used in a Pair; C0 ...

Page 15

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY REGISTER TIMING RESET DCS CSR CLK CLK D1 - D14 Q1 - Q14 (1) PAR_IN PPO (not used) QERR Timing Diagram for the First SSTUB32866B (1:2 Register-B Configuration) Device Used in a Pair; ...

Page 16

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST CIRCUITS AND WAVEFORMS (V CLK Inputs LVCMOS RESET Input t INACT I DD 10% Voltage and Current Waveforms Inputs Active and Inactive Times t W Input V ICR Voltage ...

Page 17

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST CIRCUITS AND WAVEFORMS (V Output Output NOTES includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz 1.8V ...

Page 18

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST CIRCUITS AND WAVEFORMS (V LVCMOS RESET Output Waveform 2 Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to RESET Timing Inputs Output Waveform 1 Voltage Waveforms: Open Drain Output High-to-Low ...

Page 19

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST CIRCUITS AND WAVEFORMS (V DUT CLK CLK Output Load Circuit: Partial-Parity-Out Voltage Waveforms Propagation Delay Times (with respect to clock inputs) LVCMOS RESET Input Output Load Circuit: Partial-Parity-Out Voltage Waveforms Propagation Delay ...

Page 20

IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY ORDERING INFORMATION XX XX IDT SSTUB Temp. Range Family Device Type XXX XX Package BFG 866B 32 74 CORPORATE HEADQUARTERS for SALES: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 San Jose, CA ...

Related keywords

74SSTUB32866BBFG datasheet
74SSTUB32866BBFG data sheet
74SSTUB32866BBFG pdf datasheet
74SSTUB32866BBFG component
74SSTUB32866BBFG part
74SSTUB32866BBFG distributor
74SSTUB32866BBFG RoHS
74SSTUB32866BBFG datasheet download