SSTU32866YH-T IDT, Integrated Device Technology Inc, SSTU32866YH-T Datasheet
SSTU32866YH-T
Specifications of SSTU32866YH-T
Related parts for SSTU32866YH-T
SSTU32866YH-T Summary of contents
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Integrated Circuit Systems, Inc. 25-Bit Configurable Registered Buffer Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM logic solution with ICS97U877 Product Features: • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality • Supports ...
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A DCKE PPO V V REF GND GND DODT QERR# GND GND GND GND F G PAR_IN RST# V ...
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General Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are ...
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Ball Assignment ...
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Block Diagram for 1:1 mode (positive logic) RST# CK CK# V REF DCKE DODT DCS# CSR Other Channels *Note: Disabled in 1:1 configuration 0850—08/27/03 ICSSSTU32866 Advance Information ...
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Block Diagram for 1:2 mode (positive logic) RST# CK CK# V REF DCKE DODT DCS# CSR Other Channels *Note: Disabled in 1:1 configuration 0850—08/27/03 ICSSSTU32866 Advance Information ...
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Parity Functionality Block Diagram CK CK# VREF DATA INPUT* PAR_IN * Register Configurations ...
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Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Supply Voltage . . . . . . . . . . ...
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Electrical Characteristics - 70° 2.5 +/-0.2V DDQ SYMBOL PARAMETERS -18mA All Inputs ...
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Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS f Clock frequency clock t Setup time S Hold time t H Hold time Notes Guaranteed by design, not 100% tested in production ...
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CK Inputs Test Point R = 100 L Test Point VCMOS RST Inp act I DD (see 10% Note 2) VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES t w Inpu t V ...
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LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT Output VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT Figure 7 — Output Slew-Rate M easurement I nfor mation (V Notes includes ...
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... Bsc 5.50 Bsc 1.30/1.50 0.80 Bsc 7.00 Bsc 4.50 Bsc 0.86/1.00 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. 10-0055C Ordering Information ICSSSTU32866yHT Example: ICS XXXX 0850—08/27/03 C Seating Seating Plane Plane T b ...