82V3280EQG IDT, Integrated Device Technology Inc, 82V3280EQG Datasheet - Page 84
82V3280EQG
Manufacturer Part Number
82V3280EQG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V3280EQG.pdf
(171 pages)
Specifications of 82V3280EQG
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Part Number:
82V3280EQG
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IN6_CNFG - Input Clock 6 Configuration
Programming Information
IDT82V3280
Address: 1AH
Type: Read / Write
Default Value: 00000011
DIRECT_DIV
5 - 4
3 - 0
Bit
7
6
7
BUCKET_SEL[1:0]
IN_FREQ[3:0]
DIRECT_DIV
LOCK_8K
Name
LOCK_8K
6
Refer to the description of the LOCK_8K bit (b6, 1AH).
This bit, together with the DIRECT_DIV bit (b7, 1AH), determines whether the DivN Divider or the Lock 8k Divider is used for
IN6:
These bits select one of the four groups of leaky bucket configuration registers for IN6:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN6:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz. (default)
0100: 25.92 MHz.
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN6, the required frequency should not be set higher than that of the input clock.
BUCKET_SEL1
DIRECT_DIV bit
5
0
0
1
1
BUCKET_SEL0
4
LOCK_8K bit
0
1
0
1
84
IN_FREQ3
3
Description
IN_FREQ2
Both bypassed (default)
2
Lock 8k Divider
Used Divider
DivN Divider
Reserved
IN_FREQ1
1
December 9, 2008
IN_FREQ0
0
WAN PLL
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