MCM20027IBMN Freescale, MCM20027IBMN Datasheet - Page 26

• Manufacturer Part Number: MCM20027IBMN
• Manufacturer: Freescale
• Type: CMOSr

Specifications of MCM20027IBMN

• Sensor Image Color Type: Monochrome
• Sensor Image Size Range: >= 480,000Pixels
• Sensor Image Size: 1280x1024Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 40C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

MOTOROLA
10.0 I
The I
with the Motorola bus (called M-Bus) that is available on
many microprocessor products. The I
rial two-wire half-duplex interface that features bidirec-
tional operation, master or slave modes, and multi-
master environment support. The clock frequency on
the system is governed by the slowest device on the
board. The SDATA and SCLK are the bidirectional data
and clock pins, respectively. These pins are open drain
and will require a pull-up resistor to VDD of 1.5 k to 10
k
The I
into the Program Control Registers in the MCM20027.
The I
trol Register for verification or test considerations. The
MCM20027 is a slave-only device that supports the
maximum clock rate (SCLK) of 100 kHz while reading or
writing only one register address per I 2 C start/stop cy-
cle. The following sections will be limited to the methods
for writing and reading data into the MCM20027 regis-
ter.
For a complete reference to I
Theory to Practice” by Dominique Paret and Carll-
Fenger, published by John Wiley & Sons, ISBN
0471962686.
10.1 MCM20027 I 2 C Bus Protocol
The MCM20027 uses the I 2 C bus to write or read one
register byte per start/stop I 2 C cycle as shown in
17
the various parts of the I 2 C protocol communications as
it applies to the MCM20027.
MCM20027 I 2 C bus communication is basically com-
posed of following parts: START signal, MCM20027
slave address (0110011
W bit, an acknowledgment signal from the slave, 8 bit
data transfer followed by another acknowledgment sig-
nal, STOP signal, Repeated START signal, and clock
synchronization.
10.2 START Signal
When the bus is free, i.e. no master device is engaging
the bus (both SCLK and SDATA lines are at logical “1”),
a master may initiate communication by sending a
START signal. As shown in
is defined as a high-to-low transition of SDATA while
SCLK is high. This signal denotes the beginning of a
new data transfer and wakes up all the slaves on the
bus.
10.3 Slave Address Transmission
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
and
(see
2
2
2
2
C is an industry standard which is also compatible
C bus can also read the data in the Program Con-
C is used to write the required user system data
C Serial Interface
Figure
page 3 3
18. These figures will be used to describe
).
b
) transmission followed by a R/
Figure
2
C, see “The I
Freescale Semiconductor, Inc.
For More Information On This Product,
17, a START signal
2
C contains a se-
2
C Bus from
Go to: www.freescale.com
Figure
The first byte of a data transfer, immediately after the
START signal, is the slave address transmitted by the
master. This is a 7-bit calling address followed by a R/
W bit. The seven-bit address for the MCM20027, start-
ing with the MSB (AD7) is 0110011
calling address on the SDATA line may only be
changed while SCLK is low as shown in
data on the SDATA line is valid on the High to Low sig-
nal transition on the SCLK line. The R/W bit following
the 7-bit tells the slave the desired direction of data
transfer:
•
•
10.4 Acknowledgment
Only the slave with a calling address that matches the
one transmitted by the master will respond by sending
back an acknowledge bit. This is done by pulling the
SDATA line low at the 9th clock (see
transmitted slave address is acknowledged, successful
slave addressing is said to have been achieved. No two
slaves in the system may have the same address. The
MCM20027 is configured to be a slave only.
10.5 Data Transfer
Once successful slave addressing is achieved, data
transfer can proceed between the master and the se-
lected slave in a direction specified by the R/W bit sent
by the calling master. Note that for the first byte after a
start signal (in
always a “0” designating a write transfer. This is re-
quired since the next data transfer will contain the reg-
ister address to be read or written.
All transfers that come after a calling address cycle are
referred to as data transfers, even if they carry sub-ad-
dress information for the slave device.
Each data byte is 8 bits long. Data may be changed only
while SCLK is low and must be held stable while SCLK
is high as shown in
on SCLK for each data bit, the MSB being transferred
first.
Each data byte has to be followed by an acknowledge
bit, which is signalled from the receiving device by pull-
ing the SDATA low at the ninth clock. So one complete
data byte transfer needs nine clock pulses. If the slave
receiver does not acknowledge the master, the SDATA
line must be left high by the slave. The master can then
generate a stop signal to abort the data transfer or a
start signal (repeated start) to commence a new calling.
1 = Read transfer, the slave transitions to a slave
transmitter and sends the data to the master
0 = Write transfer, the master transmits data to the
slave
Figure 17
Figure
Revision 8.4 - 24 Oct 2002 :
and
17. There is one clock pulse
Figure
ImageMOS
ImageMOS
b
. The transmitted
18), the R/W bit is
Figure
Figure
17). If a
17. The
MCM20027
26