MCM20027IBMN Freescale, MCM20027IBMN Datasheet - Page 22

• Manufacturer Part Number: MCM20027IBMN
• Manufacturer: Freescale
• Type: CMOSr

Specifications of MCM20027IBMN

• Sensor Image Color Type: Monochrome
• Sensor Image Size Range: >= 480,000Pixels
• Sensor Image Size: 1280x1024Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 40C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

MOTOROLA
9.0 Sensor Output/Input Signals
9.1 Start Of Data Capture (SYNC)
This signal is utilized by the sensor to indicate the start
of integration (data capture) in Single Frame Rolling
Shutter capture mode (SFRS). For more info refer to
Figure 15, on page
16, on page
by the sensor or be driven via Pin # 46 of the sensor
(see
is generated internally or externally, as well as other
settings to this signal, refer to
register, (Table 33), on page
9.2 Start Of Row Readout (SOF)
This signal triggers/indicates the start of Row Readout
of the frame. This signal is an Output and can be read
via Pin # 48 of the sensor (see
The SOF signal delay as well as its length can be set by
the user via
57
(Table 50), on page
the use of the SOF signal refer to
page
,Figure 8, on page 12
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ADC[9:0]
and
MCLK
SYNC
HCLK
VCLK
Figure 20, on page
SOF
22,
SOF & VCLK Signal Length Control Register,
Figure 6, on page
24. This signal can be generated internally
SOF Delay Register, (Table 48), on page
22,
Figure 15.
57. For timing diagrams depicting
and
Figure 8, on page 12
67). To set whether the signal
t
drhclk
Figure 16, on page
11,
t
50.
dadc
t
Sync and Strobe Control
susync
t
Figure 20, on page
dvclk
Pixel Data Bus Iinterface Timing Specifications (see Table Below)
Freescale Semiconductor, Inc.
t
Figure 7, on page 11
dsof
For More Information On This Product,
Figure 15, on
t
hsync
Go to: www.freescale.com
and
24.
Figure
t
dfhclk
67).
9.3 Horizontal Data SYNC (VCLK)
This signal triggers the Readout of the sequential rows
of the frame. This signal is an Output and can be read
via Pin # 44 of the sensor (see
The VCLK signal delay in relation to SOF, as well as its
length can be set by the user via
(Table 49), on page 57
Control Register, (Table 50), on page
agrams depicting the use of the VCLK signal refer
ure 15, on page
page 11 ,Figure 8, on page 12
page
9.4 Data Valid (HCLK)
This signal triggers/indicates a single active pixel data
has been readout (eg: Column 5 of Row 10 data has
been read out). This signal is an Output and can be
read via Pin # 45 of the sensor (see
page
via
timing diagrams depicting the use of the HCLK signal
refer to
Figure 7, on page 11
HCLK Delay Register, (Table 54), on page
24.
67). The HCLK signal delay can be set by the user
Figure 15, on page
22,
Figure 6, on page
,and
and
Revision 8.4 - 24 Oct 2002:
Figure 8, on page
SOF & VCLK Signal Length
22,
Figure 20, on page
and
Figure 6, on page
ImageMOS
ImageMOS
VCLK Delay Register,
Figure 16, on
Figure 20, on
57. For timing di-
11,
Figure 7, on
12.
60. For
MCM20027
toFig-
11,
67).
22