CYIL1SN3000AA-GZDC Cypress Semiconductor Corp, CYIL1SN3000AA-GZDC Datasheet - Page 36

• Manufacturer Part Number: CYIL1SN3000AA-GZDC
• Description: Image Sensor Monochrome CMOS 1696x1710Pixels 369-Pin uPGA
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOSr

Specifications of CYIL1SN3000AA-GZDC

• Sensor Image Color Type: Monochrome
• Operating Supply Voltage (typ): 2.5V
• Operating Temp Range: 0C to 60C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Package: 369uPGA
• Image Size: 1696x1710 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 60 °C
• Operating Supply Voltage: 2.25 to 2.75 V
• Lead Free Status / RoHS Status: Compliant

Global Shutter Mode
In a global shutter, light integration occurs on all pixels in parallel,
although subsequent readout is sequential.
integration and readout sequence for the global shutter. All pixels
are light sensitive at the same period of time. The whole pixel
Global Pipeline Shutter
The timing of the sensor consists of two parts. The first part is
related to the exposure time and the control of the pixel. The
second part is related to the read out of the image sensor.
Integration and readout are in parallel or triggered. In the first
case, the integration time of frame I is ongoing during the readout
of frame I-1.
The readout of every frame starts with a FOT, during which the
analog value on the pixel diode is transferred to the pixel memory
Document Number: 001-44335 Rev. *C
Figure 19
shows this parallel timing structure.
Figure 18
Figure 18. Global Shutter Operation
Figure 19. Global Readout Timing
PRELIMINARY
shows the
core is reset simultaneously, and after the integration time, all
pixel values are sampled together on the storage node inside
each pixel. The pixel core is read out line by line after integration.
Note that the integration and readout cycle can occur in parallel
or in sequential mode (pipelined or triggered).
element. After this FOT, the sensor is read out line by line. The
read out of every line starts with a ROT, during which the pixel
value is put on the column lines. The pixels are selected in
groups of 32 (kernel). The internal timing is generated by the
sequencer. LUPA3000 works in slave mode, the integration
timing is directly controlled over two external pins (Exposure 1
and Exposure 2) but the readout timing is still controlled by the
sequencer.
CYIL1SN3000AA
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