CYIL1SN3000AA-GZDC Cypress Semiconductor Corp, CYIL1SN3000AA-GZDC Datasheet - Page 15

• Manufacturer Part Number: CYIL1SN3000AA-GZDC
• Description: Image Sensor Monochrome CMOS 1696x1710Pixels 369-Pin uPGA
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOSr

Specifications of CYIL1SN3000AA-GZDC

• Sensor Image Color Type: Monochrome
• Operating Supply Voltage (typ): 2.5V
• Operating Temp Range: 0C to 60C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Package: 369uPGA
• Image Size: 1696x1710 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 60 °C
• Operating Supply Voltage: 2.25 to 2.75 V
• Lead Free Status / RoHS Status: Compliant

Table 11. LVDS Driver Specifications
Output trace characteristics affect the performance of the LUPA 3000 interface. Use controlled impedance traces to match trace
impedance to the transmission medium. The best practice regarding noise coupling and reflections is to run the differential pairs close
together. Limit skew due to receiver end limitations and for reasons of EMI reduction. Matching the differential traces is very important.
Common mode and interconnect media specifications are identical to LVDS receiver specifications.
Table 12. LVDS Receiver Specifications
Document Number: 001-44335 Rev. *C
|V
|V
V
d|V
I
I
t
|V
d|V
ZT
ZC(f)
I
t
t
t
t
t
t
f
f
I
I
Z
|V
V
T
Notes
SA
SAB
r
OFF
SKD1
SKD2
SKCD1
SKCD2
jit_rms
jit_det
MAX
MIN
IA
IA
8. The driver output swing is tuned through the LVDS driver bias current settings in the SPI register. This feature is also used to reduce the power consumption.
9. Jitter with reference to LUPA 3000 input clock
10. This is from LVDS point of view, from sensor point of view fMIN is 4 MHz (about 10 fps). At lower speeds dark current and storage node leakage starts influencing
OS
T
IH
JIT_TOT
t
T
T
ring
ID
, I
-I
f
Parameter
/I
Parameter
|
(1)|–|V
, V
OS
OS
Alternatively, decrease the termination resistor to boost the speed and keep the swing identical by increasing the bias current.
the image quality.
IB
|
IB
[7]
SB
[10]
|
|
|
[9]
IL
[8]
T
(0)|
Input current
Input current unbalance
Required external termination
Differential input
minimum and maximum input voltages
Total jitter at LUPA 3000 clock input
Differential logic voltage
Delta differential voltage
Common mode offset
Difference in common mode voltage for logic 1 and 0
Output currents in short to ground condition
Output current in differential short condition
Differential rise and fall time
Differential over and undershoot
Dynamic common mode offset
Termination resistance
Characteristic impedance of the interconnect
Offstate current
Differential skew
Differential channel to channel skew
Differential clock out to data skew
Differential clock in to data skew
Random jitter
Deterministic jitter
Maximum operating frequency
Minimum operating frequency
Description
Description
PRELIMINARY
Specification (guaranteed by design)
Specification (guaranteed by design
1.125
Min
100
Min
400
247
90
90
90
0
1
Typ
100
1.25
Typ
350
100
CYIL1SN3000AA
0.2*V
1.375
Max
132
Max
0.25
600
500
2.4
454
250
150
132
132
500
206
20
0.5
50
50
24
12
10
50
6
1
3
T
Page 15 of 61
Units
mV
MHz
MHz
Units
mV
mV
mV
mA
mA
µA
ps
ns
ns
ns
ns
ps
ps
mV
Ω
Ω
µA
µA
V
V
ps
Ω
V
PP
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