AT94K10AL-25DQC Atmel, AT94K10AL-25DQC Datasheet - Page 79

• Manufacturer Part Number: AT94K10AL-25DQC
• Manufacturer: Atmel

Specifications of AT94K10AL-25DQC

• Device System Gates: 10000
• Propagation Delay Time: 12.7ns
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Not Compliant

4.22
4.22.1
4.22.2
4.22.2.1
1138I–FPSLI–1/08
AVR Reset Register
Boundary-scan Chain
Boundary-scan Specific JTAG Instructions
EXTEST; $0
The AVR Reset Register is a Test Data Register used to reset the AVR. A high value in the
Reset Register corresponds to pulling the external AVRResetn Low. The AVR is reset as long as
there is a high value present in the AVR Reset Register. Depending on the Bit settings for the
clock options, the CPU will remain reset for a Reset Time-Out Period after releasing the AVR
Reset Register. The output from this Data Register is not latched, so the reset will take place
immediately, see
Figure 4-19. Reset Register
The Boundary-scan Chain has the capability of driving and observing the logic levels on the
AVR’s digital I/O pins.
See
The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG
instructions useful for Boundary-Scan operation. Note that the optional HIGHZ instruction is not
implemented.
As a definition in this data sheet, the LSB is shifted in and out first for all shift registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which data register is selected as path between TDI and TDO for each instruction.
Mandatory JTAG instruction for selecting the Boundary-Scan Chain as Data Register for testing
circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output
Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip
connections, the interface between the analog and the digital logic is in the scan chain. The con-
tents of the latched outputs of the Boundary-Scan chain are driven out as soon as the JTAG IR-
register is loaded by the EXTEST instruction.
The active states are:
“Boundary-scan Chain” on page 80
From other internal and
external reset sources
Figure
ClockDR · AVR_RESET
4-19.
From
TDI
D
for a complete description.
Q
TDO
To
AT94KAL Series FPSLIC
Internal AVR Reset
79