AT94K10AL-25DQC Atmel, AT94K10AL-25DQC Datasheet - Page 32
AT94K10AL-25DQC
Manufacturer Part Number
AT94K10AL-25DQC
Description
Manufacturer
Atmel
Datasheet
1.AT94K10AL-25DQC.pdf
(204 pages)
Specifications of AT94K10AL-25DQC
Device System Gates
10000
Propagation Delay Time
12.7ns
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Manufacturer
Quantity
Price
Part Number:
AT94K10AL-25DQC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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32
AT94KAL Series FPSLIC
Table 3-7.
Bit
SCR31
SCR32 - SCR34
SCR35
SCR36
SCR37
SCR38
SCR39
SCR40 - SCR41
SCR 42 -
SCR47
SCR48
SCR49
SCR50
SCR51
SCR52
SCR53
FPSLIC System Control Register (Continued)
Description
0 = Disable I/O Tri-state
1 = I/O Tri-state During (Internal and External) Configuration Download.
SCR31 forces all user defined I/O pins to go tri-state during configuration
download. Tri-state is released at the end of configuration download on the rising
edge of CON, if set.
Reserved
0 = AVR Reset Pin Disabled
1 = AVR Reset Pin Enabled (active Low Reset)
SCR35 allows the AVR Reset pin to reset the AVR only.
0 = Protect AVR Program SRAM
1 = Allow Writes to AVR Program SRAM (Excluding Boot Block)
SCR36 protects AVR program code from writes by the FPGA.
0 = AVR Program SRAM Boot Block Protect
1 = AVR Program SRAM Boot Block Allows Overwrite
0 = (default) Frame Clock Inverted to AVR Data/Program SRAM
1 = Non-inverting Clock Into AVR Data/Program SRAM
Reserved
SCR41 = 0, SCR40 = 0 16 Kbytes x 16 Program/4 Kbytes x 8 Data
SCR41 = 0, SCR40 = 1 14 Kbytes x 16 Program/8 Kbytes x 8 Data
SCR41 = 1, SCR40 = 0 12 Kbytes x 16 Program/12 Kbytes x 8 Data
SCR41 = 1, SCR40 = 1 10 Kbytes x 16 Program/16 Kbytes x 8 Data
SCR40 : SCR41 AVR program/data SRAM partitioning (set by using the AT94K
Device Options in System Designer).
Reserved
0 = EXT-INT0 Driven By Port E<4>
1 = EXT-INT0 Driven By INTP0 pad
SCR48 : SCR53 Defaults dependent on package selected.
0 = EXT-INT1 Driven By Port E<5>
1 = EXT-INT1 Driven By INTP1 pad
SCR48 : SCR53 Defaults dependent on package selected.
0 = EXT-INT2 Driven By Port E<6>
1 = EXT-INT2 Driven By INTP2 pad
SCR48 : SCR53 Defaults dependent on package selected.
0 = EXT-INT3 Driven By Port E<7>
1 = EXT-INT3 Driven By INTP3 pad
SCR48 : SCR53 Defaults dependent on package selected.
0 = UART0 Pins Assigned to Port E<1:0>
1 = UART0 Pins Assigned to UART0 pads
SCR48 : SCR53 Defaults dependent on package selected.
0 = UART1 Pins Assigned to Port E<3:2>
1 = UART1 Pins Assigned to UART1 pads
SCR48 : SCR53 Defaults dependent on package selected.
On packages less than 144-pins, there is reduced access to AVR ports. Port D is
not available externally in the smallest package and Port E becomes dual-purpose
I/O to maintain access to the UARTs and external interrupt pins. The Pin List (East
Side) on
page 188
shows exactly which pins are available in each package.
1138I–FPSLI–1/08
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