SAA7113HV2 NXP Semiconductors, SAA7113HV2 Datasheet - Page 52
SAA7113HV2
Manufacturer Part Number
SAA7113HV2
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7113HV2.pdf
(75 pages)
Specifications of SAA7113HV2
Video Resolution (max)
720Pixels
Pin Count
44
Package Type
PQFP
Lead Free Status / RoHS Status
Compliant
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Philips Semiconductors
9397 750 14232
Product data sheet
9.2.26 Subaddresses 41h to 57h
9.2.27 Subaddress 58h
Table 62:
[1]
Table 63:
Table 64:
LCR register 2 to 24 (subaddresses 41h
to 57h)
WST625
CC625
VPS
WSS
WST525
CC525
Test line
Intercast
General
text
VITC625
Reserved
NABTS
Japtext
JFS
Active
video
FOFF
0
1
Slicer set (subaddress 58h)
Programmable framing code
Default
The assignment of the upper and lower nibbles to the corresponding field depends on the setting of FOFF
(subaddress 5Bh, bit 7); see
LCR register 2 to 24 (subaddresses 41h to 57h); see
Setting of FOFF
Framing code for programmable data types
teletext EuroWST, CCST
European closed caption
video programming service
wide screen signalling bits
US teletext (WST)
US closed caption (line 21)
video component signal, VBI
region
oversampled CVBS data
teletext
VITC/EBU time codes
(Europe)
VITC/SMPTE time codes
(USA)
-
US NABTS
MOJI (Japanese)
Japanese format switch
(L20/22)
video component signal,
active video region (default)
Rev. 02 — 9 May 2005
Table
D7 to D4
field 1
field 2
63.
Framing code
27h
001
9951h
1E3C1Fh
27h
001
-
-
programmable
programmable
programmable
-
-
programmable (A7h)
programmable
-
Control bits D7 to D0
FC7 to FC0
40h
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
D3 to D0
field 2
field 1
9-bit video input processor
D7 to D4
DT3 to DT0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 7
SAA7113H
[1]
D3 to D0
DT3 to DT0
0000
0001
0010
0011
0100
0101
0110
0111
1011
1100
1111
1000
1001
1010
1101
1110
52 of 75
[1]
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