SAA7113HV2 NXP Semiconductors, SAA7113HV2 Datasheet - Page 45
SAA7113HV2
Manufacturer Part Number
SAA7113HV2
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7113HV2.pdf
(75 pages)
Specifications of SAA7113HV2
Video Resolution (max)
720Pixels
Pin Count
44
Package Type
PQFP
Lead Free Status / RoHS Status
Compliant
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Philips Semiconductors
9397 750 14232
Product data sheet
9.2.17 Subaddress 10h
Table 44:
Table 45:
Table 46:
[1]
Table 47:
Table 48:
Automatic chrominance gain control ACGC
On
Programmable gain via CGAIN6 to CGAIN0
Luminance delay compensation
(steps in 2/LLC)
...0...
...3
Control bit D3
VRLN
Length
Line number
Field 1
Field 2
Fine position of HS (steps in 2/LLC)
0
1
2
3
V-flag generation in SAV/EAV-codes
Standard ITU-R BT 656 format
V-flag in SAV/EAV is generated by VREF
V-flag in SAV/EAV is generated by data-type
Reserved
4...
The numbers given in parenthesis refer to ITU line counting.
[1]
[1]
Chrominance gain control subaddress 0Fh (D7)
Format/delay control subaddress 10h (D2 to D0)
VREF pulse position and length VRLN subaddress 10h (D3)
Fine position of HS HDEL0 and HDEL1 subaddress 10h (D5 and D4)
Output format selection OFTS0 and OFTS1 subaddress 10h (D7 and D6); see
Table 9
first
19 (22)
282 (285)
and
Table 10
240
Rev. 02 — 9 May 2005
0
VREF at 60 Hz 525 lines
last
258 (261)
521 (524)
Control bits D2 to D0
YDEL2
1
0
0
first
18 (21)
281 (284)
Control bits D5 and D4
HDEL1
0
0
1
1
Control bits D7 and D6
OFTS1
0
0
1
1
242
1
last
259 (262)
522 (525)
YDEL1
0
0
1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
first
24
337
9-bit video input processor
VREF at 50 Hz 625 lines
286
0
SAA7113H
last
309
622
HDEL0
0
1
0
1
OFTS0
0
1
0
1
YDEL0
0
0
1
Control bit D7
ACGC
0
1
first
23
336
288
1
last
310
623
45 of 75
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