MCIMX257CJM4A Freescale, MCIMX257CJM4A Datasheet - Page 64

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MCIMX257CJM4A

Manufacturer Part Number
MCIMX257CJM4A
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX257CJM4A

Lead Free Status / RoHS Status
Compliant

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3.7.6.1.3
The following diagrams and tables specify timing related to the SDRAMC module, which interfaces with
DDR2 SDRAM.
Table 48
differential slew rate of 2 V/ns. For additional values, use
DDR2-400, DDR2-533.”
64
DDR1
DDR2
DDR3
ID
SDCLK
SDCLK
ADDR
RAS
CAS
provides values for a command/address slew rate of 1 V/ns and an SDCLK, SDCLK_B
WE
CKE
CS
DDR6
DDR4
DDR4
DDR2 SDRAM–Specific Parameters
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
ROW/BA
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
Figure 31. DDR2 SDRAM Basic Timing Parameters
DDR5
Table 48. DDR2 SDRAM Timing Parameter Table
DDR5
Parameter
DDR7
DDR4
DDR4
COL/BA
DDR4
DDR5
DDR5
Table
DDR1
DDR3
49, “tlS, tlH Derating Values for
Symbol
t
t
t
CH
CL
CK
DDR2
Min.
0.45
0.45
7.5
DDR2-400
Freescale Semiconductor
Max.
0.55
0.55
8
Unit
t
t
ns
CK
CK

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