MCIMX257CJM4A Freescale, MCIMX257CJM4A Datasheet - Page 113

• Manufacturer Part Number: MCIMX257CJM4A
• Manufacturer: Freescale

Specifications of MCIMX257CJM4A

• Lead Free Status / RoHS Status: Compliant

assertion of soc is detected. Thus, if the soc signal is continuously asserted, the ADC undergoes successive
conversion cycles and achieves the maximum sampling rate. If soc is negated, no conversion is initiated.
The output data can be read from adcout11...adcout0, and is available tdata nanoseconds after the rising
edge of eoc. The reset signal and the digital signals controlling the analog switches (ypsw, xpsw, ynsw,
xnsw) are totally asynchronous.
The following conditions are necessary to guarantee the correct operation of the ADC:
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The input multiplexer selection (selin11…selin0) is stable during both the last clock cycle (14
and the first clock cycle (1
selection during clock cycles 2 to 13.
The references are stable during clock cycle 1 to 13. The best way to guarantee this is to make the
reference multiplexer selection (selrefp and selrefn) before issuing an soc pulse and changing it
only after an eoc pulse has been acquired, during the last clock cycle (14).
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
st
). The best way to guarantee this is to make the input multiplexer
Figure 82. Start-up Sequence
th
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