NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 61

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Documentation Changes
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Workaround:
Affected Docs: Intel
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Affected Docs: Intel
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Affected Docs: Intel
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Affected Docs: Intel
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Affected Docs: Intel
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Affected Docs: Intel
Specification Update
Table 236 shows incorrect description for tWDL field
tWDL field (bits 13:12) shows ‘00’ equals DDR-II Type only.
Should state ‘DDR-I Type only’
Processor Device ID should be removed
Page 739, top of the table shows Processor Device ID Register.
This register is no longer valid and should be removed, see specification clarification #
Core Performance Monitoring Unit (CPMON) section is incorrect
Incorrect and incomplete information regarding the Core Performance Monitoring Unit.
Changes include additional control registers (Interrupt, Overflow, Event) and two more counter
(PMN2 and PMN3). See the Intel XScale
manual as ‘XSC2’ core.
UART FIFO Occupancy Register is read only
Table 312 shows UART FIFO Occupancy register (UxFOR) as ‘read/write’.
Needs to be changed to ‘read-only’.
Refresh Frequency Register table is incorrect
The values listed in Table 230 are incorrect.
Should be as follows:
333 MHz: 500h (7.8 µs value); A00h (15.6 µs value)
400 MHz: 600h (7.8 µs value); C00h (15.6 µs value)
PBI interrupt should be removed
PBI interrupt should not be included in the 80331 documentation.
All references to the Peripheral Bus Unit Error Interrupt should be removed. This can be found in
Figure 116, INTCTL1.21, INTSTR1.21, IINTSRC1.21, FINTSRC1.21 and IPR3.
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80331 I/O Processor Developer’s Manual
80331 I/O Processor Developer’s Manual
80331 I/O Processor Developer’s Manual
80331 I/O Processor Developer’s Manual
80331 I/O Processor Developer’s Manual
80331 I/O Processor Developer’s Manual
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Core Developer’s Manual (273473), referred to in the
Intel
Documentation Changes
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80331 I/O Processor
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