NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 25

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

25.
Problem:
Implication:
Workaround:
Status:
26.
Problem:
Implication:
Workaround:
Status:
Specification Update
Note: When neither of these are used by the board vendors during manufacturing testing, there is no issue.
Boundary scan multi-chip module implementation
The 80331 is not BSDL-compliant for the SAMPLE and BYPASS instructions specified by the
JTAG specification 1149.1. It is compliant for most board-level testing. When boards are tested for
opens and shorts, the 80331 BSDL can define the boundary scan length as +1 to encompass the
BYPASS register in the Intel XScale
When doing ID, SAMPLE, or BYPASS, the Intel XScale
from TDI to TDO one flop longer than the specification requires, which could cause canned
software to error.
Intel can provide two BSDL files which allow opens and shorts testing, as long as it does not test
the ID and BYPASS instructions. One covers the Intel XScale
I/O processor, with the exception that both instruction sets are reduced from 14 to 7, since they are
operating independently.
No Fix. Not to be fixed. See the
Auto refresh command also generates a Precharge All command on DDR
bus
When an auto refresh command is issued to the MCU SDRAM Initialization Register (write 0x6 to
SDIR) the hardware state machine executes a precharge all command and then an auto refresh
command.
Some DIMMs may fail to initialize.
There is no way to decouple the precharge all and auto refresh commands in the MCU. However,
the DCAL can issue an auto refresh command, which can be used instead to issue the auto refresh
for initialization.
For both DDRI and DDRII initialization sequences, there are two back-to-back AutoRefresh
(ARF) commands issued to the DIMM (accomplished by writing 0x6 to MCU_SDIR
0xFFFF_E500 twice). This sequence is replaced by writing to the DCAL Control and Status
Register (DCALSR) 0xFFFF_F500 to issue an AutoRefresh to each Chip Select, thus there are four
writes to the DCALSR as opposed to the previous two writes to MCU_SDIR. The exact address
and data values are as follows:
ADDRESS
0xFFFF_F500 0x8000_0001 -- ARF to CS[0]
0xFFFF_F500 0x8000_0001 -- ARF to CS[0]
0xFFFF_F500 0x8010_0001 -- ARF to CS[1]
0xFFFF_F500 0x8010_0001 -- ARF to CS[1]
No Fix. Not to be fixed. See the
WRITE_DATA
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
®
core (therefore not visible).
NOTE
®
core BYPASS register makes the path
®
core unit and the other one for the
Intel
®
80331 I/O Processor
9.
9.
Non-Core Errata
25