MC9328MX21VG Freescale, MC9328MX21VG Datasheet - Page 28

• Manufacturer Part Number: MC9328MX21VG
• Manufacturer: Freescale

Specifications of MC9328MX21VG

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Specifications
Figure 13
asserted, the BMI will detect the BMI_WAIT signal on every falling edge of the Int_Clk. When it detected
the high level of the BMI_WAIT, the BMI_READ will be negated after 1+WS Int_Clk period. If the
BMI_WAIT is always high or already high before BMI_READ is asserted, this timing will same as
without WAIT signal. So the BMI_READ will be asserted at least for 1+WS Int_Clk period.
3.9
To use the internal transmit (TX) and receive (RX) data FIFOs when the CSPI1 module is configured as a
master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY
signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period
Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either CSPI1
or CSPI2. When the CSPI1 module is configured as a slave, the user can configure the SPI 1 Control
Register (CONTROLREG1) to match the external CSPI master’s timing. In this configuration, SS
28
Figure 12. Memory Interface Master Mode, BMI Write to External Slave Device Timing with Wait Signal
Figure 13. Memory Interface Master Mode, BMI Read to External Slave Device Timing with Wait Signal
(reference only)
(reference only)
CSPI Timing Diagrams
shows the BMI read timing when the WAIT bit is set. As write timing, when the BMI_READ is
BMI_CLK/CS
Int_Clk
BMI_CLK/CS
BMI_WRITE
BMI_D[15:0]
BMI_WRITE
BMI_D[15:0]
BMI_READ
BMI_READ
BMI_WAIT
BMI_WAIT
Int_Clk
(MMD_MODE_SEL=0, MASTER_MODE_SEL=1,WAIT=1)
(MMD_MODE_SEL=0, MASTER_MODE_SEL=1,WAIT=1)
MC9328MX21 Technical Data, Rev. 3.4
TXD_a
RXD_a
1+ws
1+ws
1+ws
1+ws
TXD_b
RXD_b
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