MC9328MX21VG Freescale, MC9328MX21VG Datasheet

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... Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2005–2008. All rights reserved. ...

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... Enhanced Multimedia Accelerator (eMMA) Pre- and Post- Process- Video Accelera- Figure 1. i.MX21 Functional Block Diagram MC9328MX21 Technical Data, Rev. 3.4 Connectivity CSPI x 3 SSI Audio Mux UART x 1-WIRE IrDA USB OTG/ 2 Memory Expansion MMC/ PCMCIA/ Memory Interface SDRAM C EIM/BMI NFC Freescale Semiconductor ...

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... MC9328MX21 Reference Manual (order number MC9328MX21RM) The Freescale manuals are available on the Freescale Semiconductor Web site at http:// www.freescale.com. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com. 1.4 ...

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... MAPBGA Lead-free 289-lead MAPBGA Lead-free 289-lead MAPBGA Lead-free 289-lead MAPBGA Lead-free MC9328MX21 Technical Data, Rev. 3.4 Operating Range ° ° -30 C–70 C ° ° -30 C–70 C ° ° -40 C–85 C ° ° -40 C–85 C ° ° -40 C– Freescale Semiconductor ...

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... Data bus signals EB0 MSB Byte Strobe—Active low external enable byte signal that controls D [31:24], shared with SDRAM DQM0. Freescale Semiconductor depends solely upon the user application, however there are a few Table 2. i.MX21 Signal Descriptions Function/Notes External Bus/Chip Select (EIM) MC9328MX21 Technical Data, Rev ...

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... Function Multiplexing Control Register in the System Control chapter. RAS SDRAM Row Address Select signal. CAS SDRAM Column Address Select signal SDWE SDRAM Write Enable signal SDCKE0 SDRAM Clock Enable 0 SDCKE1 SDRAM Clock Enable 1 SDCLK SDRAM Clock 6 Function/Notes Bootstrap SDRAM Controller MC9328MX21 Technical Data, Rev. 3.4 Freescale Semiconductor ...

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... JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is multiplexed with 1-Wire, therefore using 1-Wire renders RTCK unusable and vice versa. CSI_D [7:0] Sensor port data CSI_MCLK Sensor port master clock Freescale Semiconductor Function/Notes Clocks and Resets JTAG CMOS Sensor Interface MC9328MX21 Technical Data, Rev. 3.4 Signal Descriptions ® ...

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... SLCDC Chip Select input signal for pass through to SLCD device. This signal is multiplexed with SSI3_TXD signal from SSI3. SLCDC2_RS SLCDC Register Select input signal for pass through to SLCD device. This signal is multiplexed with SSI3_RXD signal from SSI3. 8 Function/Notes LCD Controller Smart LCD Controller MC9328MX21 Technical Data, Rev. 3.4 Freescale Semiconductor ...

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... PC_WAIT PCMCIA Wait input signal to extend current access. This signal is multiplexed with NFIO[5] signal of NF. PC_READY PCMCIA Ready input signal indicates card is ready for access. Multiplexed with NFIO[4] signal of NF. Freescale Semiconductor Function/Notes Bus Master Interface (BMI) External DMA NAND Flash Controller PCMCIA Controller MC9328MX21 Technical Data, Rev ...

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... Master Out/Slave In signal. This signal is multiplexed with SD1_CMD. CSPI3_MISO Master In/Slave Out signal. This signal is multiplexed with SD1_D0. CSPI3_SS Slave Select (Selectable polarity) signal multiplexed with SD1_D3. CSPI3_SCLK Serial Clock signal. This signal is multiplexed with SD1_CLK. 10 Function/Notes CSPI MC9328MX21 Technical Data, Rev. 3.4 Freescale Semiconductor ...

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... USB Host2 Transmit Data Plus output signal. This signal is multiplexed with CSPI2_MOSI of CSPI2. USBH2_TXDM USB Host2 Transmit Data Minus output signal. This signal is multiplexed with CSPI2_MISO of CSPI2. USBH2_OE USB Host2 Output Enable signal. This signal is multiplexed with CSPI2_SCLK of CSPI2. Freescale Semiconductor Function/Notes General Purpose Timers USB On-The-Go MC9328MX21 Technical Data, Rev. 3.4 ...

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... Serial clock signal which is output in master or input in slave SSI1_TXD Transmit serial data SSI1_RXD Receive serial data SSI1_FS Frame Sync signal which is output in master and input in slave 12 Function/Notes Secure Digital Interface UARTs – IrDA/Auto-Bauding 2 S protocol and AC97) MC9328MX21 Technical Data, Rev. 3.4 Freescale Semiconductor ...

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... System Control chapter must be used in conjunction with programming the GPIO multiplexing (to select the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are available. NVDD Noisy Supply for the I/O pins. There are six (6) I/O voltages, NVDD1 through NVDD6. NVSS Noisy Ground for the I/O pins Freescale Semiconductor Function/Notes 1-Wire ...

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... Range” (Table Table 3. Maximum Ratings Symbol QVDD QVDDX max, max NVDD VDDA max, max V Imax T storage MC9328MX21 Technical Data, Rev. 3.4 3) may cause 4) is not implied. Exposure to Min Max -0.3 2.1 -0.3 3.3 1 -0.3 VDD + 0.3 -55 150 Freescale Semiconductor Units ...

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... Low-level output voltage High-level output current, slow I/O High-level output current, fast I/O Low-level output current, slow I/O Low-level output current, fast I/O Schmitt trigger Positive–input threshold Schmitt trigger Negative–input threshold Hysteresis Freescale Semiconductor Symbol VK DVK, DVM T A CVK, CVM ...

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... Typ Max Units 5 pF – – Symbol Typ Max Units 120 – QVDD QVDDX I 8 – NVDD1 through 6.6 – NVDD6 VDDA I STBY 1 – 3.0 ° – 700 ° 320 – L Freescale Semiconductor Units μA μ μA μ ...

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... Parameter Reference clock frequency range Pre-divider output clock frequency range Double clock frequency range Pre-divider factor (PD) Total multiplication factor (MF) Freescale Semiconductor Maximum I/O Loading at 1 Table 9. 32k/26M Oscillator Signal Timing Best Case Typical Worst Case ...

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... Figure 2 and 3 7 cycles @ CLK32 4 14 cycles @ CLK32 Freescale Semiconductor Unit – – – T ref T ref T ref T ref 2•T dck ns mW (Avg) ...

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... RSSR settings) becomes the current highest priority channel. The external device using the External DMA request should keep its request asserted until it is serviced by the DMAC. One External DMA request will initiate one DMA burst. Freescale Semiconductor 5 Table 12. Reset Module Timing Parameters MC9328MX21 Technical Data, Rev ...

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... External device Data written to External device NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform. Figure 5. Safe Maximum Timings for External Request De-Assertion 20 t min_assert t max_req_assert t max_read MC9328MX21 Technical Data, Rev. 3.4 Figure 4 and t max_write Freescale Semiconductor ...

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... It puts data into the data bus and enables the data out on the rising edge of BMI_CLK BMI_WRITE is logic high. The BMI_READ_REQ is negated one hclk cycle after the BMI_CLK/ CS rising edge of last data read. The MMD cannot issues read command when BMI_READ_REQ is low (no data in TxFIFO). Freescale Semiconductor 3.0 V WCS BCS 8 hclk + 8 ...

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... WRITE is logic low, it latches data into the RxFIFO on each falling edge of BMI_CLK/CS signal Tdh Tds TxD1 TxD2 Ts Symbol Minimum Typical 1T 33 Trh 6 Tds 6 Tdh 6 MC9328MX21 Technical Data, Rev. 3.4 Trh Last TxD Maximum Unit – – ns – – ns – – Freescale Semiconductor ...

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... It is recommended that the MMD do not change the BMI_WRITE signal from high to low when the BMI_READ_REQ is asserted. If user writes data to the TxFIFO when the BMI_WRITE is low, the BMI will drive BMI_CLK/CS out once the BMI_WRITE is changed from low to high. Freescale Semiconductor Can be asserted any time RxD1 ...

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... BMI_WRITE signal can not be negated when the WRITE operation is proceeding Tdh Tds TxD1 TxD2 Symbol Minimum Typical Tds 2 Tdh 2 Trh 2 MC9328MX21 Technical Data, Rev. 3.4 Trh Last TxD Maximum Unit – – – Freescale Semiconductor ...

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... BMI_WRITE is logic high. The D_EN signal remains active only while BMI_CLK logic low and BMI_WRITE is logic high. Each rising edge of BMI_CLK/CS will determine if data should be latched to RxFIFO from the data bus. Freescale Semiconductor Total has COUNT+1 clocks in one burst Can be asserted any time ...

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... WRITE and CLK/CS signals. 26 Ttds Trdh Ttdh TxD RxD Read Write BMI BMI Symbol Minimum Typical Trdh 3 Ttds 6 Ttdh 6 Trh 6 MC9328MX21 Technical Data, Rev. 3.4 Trh Last TxD Read BMI Maximum Unit – – ns – – ns – – ns – – – Freescale Semiconductor ...

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... Int_Clk. When it detected the high level of the BMI_WAIT, the BMI_WRITE will be negated after 1+WS Int_Clk period. If the BMI_WAIT is always high or already high before BMI_WRITE is asserted, this timing will same as without WAIT signal. So the BMI_WRITE will be asserted at least for 1+WS Int_Clk period. Freescale Semiconductor 1+ws Last TxD TxD2 ...

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... CSPI2. When the CSPI1 module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the external CSPI master’s timing. In this configuration 1+ws 1+ws TXD_a 1+ws 1+ws RXD_a MC9328MX21 Technical Data, Rev. 3.4 TXD_b RXD_b Freescale Semiconductor ...

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... Figure 16. Master CSPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 17. Slave CSPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO Figure 18. Slave CSPI Timing Diagram FIFO Advanced by SS Rising Edge Freescale Semiconductor MC9328MX21 Technical Data, Rev. 3.4 Specifications ...

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... Tsclk + WAIT Figure 19. SCLK to LD Timing Diagram Table 20. LCDC SCLK Timing Parameters Minimum MC9328MX21 Technical Data, Rev. 3.4 through Figure 18 Maximum Unit 1 – – ns – ns – – ns – ns – 3.0 ± 0.3V Maximum 2000 – – Freescale Semiconductor Unit ...

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... Ts is the SCLK period. • VSYN, HSYN and OE can be programmed as active high or active low. In • SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In always active. • XMAX is defined in number of pixels in one line. Freescale Semiconductor Non-display region XMAX ...

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... Falling of PS aligns with rising edge of CLS. • REV toggles in every HSYN period. 32 XMAX Figure 21. Sharp TFT Panel Timing Table 22. Sharp TFT Panel Timing Minimum – MC9328MX21 Technical Data, Rev. 3.4 D320 Value 1 HWAIT1+1 HWAIT2 + 4 CLS_RISE_DELAY+1 CLS_HI_WIDTH+1 PS_RISE_DELAY REV_TOGGLE_DELAY+1 Freescale Semiconductor Unit ...

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... VSYN, HSYN and SCLK can be programmed as active high or active low. In active high. • When CSTN mode or monochrome mode with bus width = Tpix = Ts. • When monochrome mode with bus width = 2, 4, and and 4 Tpix respectively. Freescale Semiconductor T1 T3 XMAX Figure 22. Non-TFT Mode Panel Timing Table 23 ...

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... RS=0 ≥ command data, RS=1≥ display data SCKPOL = 0, CSPOL = MSB T6 RS=0 ≥ command data, RS=1≥ display data SCKPOL = 1, CSPOL = MSB T6 RS=0 ≥ command data, RS=1≥ display data SCKPOL = 0, CSPOL = 1 Figure 23. SLCDC Serial Transfer Timing MC9328MX21 Technical Data, Rev. 3 LSB LSB LSB LSB Freescale Semiconductor ...

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... Register select hold time LCD_CLK LCD_RS LCD_CS LCD_DATA[15:0] LCD_CLK LCD_RS LCD_CS LCD_DATA[15:0] Symbol Description T1 Pixel clock period T2 Data setup time T3 Data hold time T4 Register select setup time T5 Register select hold time Freescale Semiconductor Table 24. SLCDC Serial Transfer Timing Description Minimum command data CSPOL = ...

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... V ± 0.3 V Max Min Max 25/5 0 25/5 400 0 400 – 10/50 – – 10/50 – 3 10/50 (5.00) – 10/50 3 14/67 (6.67) – 10/50 – 5/5 – – 5/5 – – 5/5 – – 5/5 – Freescale Semiconductor Unit MHz kHz ...

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... SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card. The other two diagrams show the separating periods N Freescale Semiconductor clock cycles. For the card address assignment, ID Figure 26 ...

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... Timing response end to next CMD start (data transfer mode) N cycles CC CRC ****** Timing of command sequences (all modes) until the card sees a stop transmission command. The AC MC9328MX21 Technical Data, Rev. 3.4 Response Content CRC Host Command Content CRC Host Command Content CRC beginning AC Freescale Semiconductor ...

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... The card sends back the CRC check result status token on the data line. If there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned. The card expects a continuous flow of data blocks configured to multiple block mode, with the flow terminated by a stop transmission command. Freescale Semiconductor N cycles CR ...

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... Specifications The stop transmission command may occur when the card is in different states. different scenarios on the bus. 40 Figure 29. Timing Diagrams at Data Write MC9328MX21 Technical Data, Rev. 3.4 Figure 30 shows the Freescale Semiconductor ...

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... Figure 30. Stop Transmission During Different Scenarios Table 28. Timing Values for Parameter MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle Freescale Semiconductor Figure 26 through Symbol Minimum NCR 2 ...

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... Figure 31. SDIO IRQ Timing Diagram CMD52 CRC Figure 32. SDIO ReadWait Timing Diagram MC9328MX21 Technical Data, Rev. 3.4 Figure 30 (Continued) Maximum – Clock cycles – Clock cycles – Clock cycles 2 Clock cycles ****** IRQ Block Data S E ****** Block Data S E Block Data E Freescale Semiconductor Unit IRQ ...

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... MHz. It should also be noted that the default NFC clock on power up is 16.63 MHz. NFCLE NFCE NFWE NFALE NFIO[7:0] Figure 33. Command Latch Cycle Timing DIagram Freescale Semiconductor Figure 36 depict the relative timing requirements among different Table 29 lists the timing parameters. The NAND Flash Controller NF1 NF2 ...

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... NF1 NF3 NF10 NF5 NF11 NF6 NF8 NF9 Data to Flash Figure 35. Write Data Latch Timing DIagram NF14 NF3 NF13 NF16 Data from Flash NF12 Figure 36. Read Data Latch Timing Diagram MC9328MX21 Technical Data, Rev. 3.4 Address NF4 NF15 NF17 Freescale Semiconductor ...

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... High is defined as 80% of signal value and low is defined as 20% of signal value. All timings are listed according to this NFC clock frequency (multiples of NFC clock period) except NF16, which is not NFC clock related. 2. The read data is generated by the NAND Flash device and sampled with the internal NFC clock. Freescale Semiconductor Table 29. NFC Target Timing Parameters Relationship to NFC ...

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... Minimum Maximum 0 45 12.29 – 9.91 – – 0.5 – 0.5 9.37 – 8.71 – MC9328MX21 Technical Data, Rev. 3 3.0 V ± 0.3 V Unit Minimum Maximum 0 45 MHz 12.29 – 9.91 – – 0.5 – 0.5 3.61 – 3.03 – Freescale Semiconductor ...

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... Table 31. SDRAM Read Cycle Timing Parameter Ref Parameter No. 1 SDRAM clock high-level width 2 SDRAM clock low-level width 3 SDRAM clock cycle time 3S CS, RAS, CAS, WE, DQM setup time 3H CS, RAS, CAS, WE, DQM hold time Freescale Semiconductor through Figure 41) and their associated tables specify the timings related COL/ ...

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... ROW/BA 8 MC9328MX21 Technical Data, Rev. 3.4 3.0 V ± 0.3 V Maximum Minimum Maximum – 2 – – 2 – – 5.4 5.4 – 6.0 6.0 – – – – – – – – – – 2 – t – RCD COL/BA 9 DATA Freescale Semiconductor Unit ...

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... Precharge cycle timing is included in the write timing diagram and t = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual. RP RCD SDCLK RAS CAS ADDR BA DQ DQM Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 3.00 3.00 7.5 3.67 2. RCD 3.41 2. Figure 40 ...

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... Figure 41. SDRAM Self-Refresh Cycle Timing Diagram 50 1.8 V ± 0.1 V Minimum Maximum 3.00 – 3.00 – 7.5 – 3.67 – 2.95 – – – RC MC9328MX21 Technical Data, Rev. 3.4 3.0 V ± 0.3 V Unit Minimum Maximum 3 – – ns 7.5 – – – – – Freescale Semiconductor ...

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... The SSI can be connected to 4 set of ports, SAP, SSI1, SSI2 and SSI3. CK Output FS (bl) Output FS (wl) Output STXD Output SRXD Input Note: SRXD input in synchronous mode only. Figure 42. SSI Transmitter Internal Clock Timing Diagram Freescale Semiconductor Figure 45 MC9328MX21 Technical Data, Rev ...

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... FS (bl) Input FS (wl) Input STXD Output SRXD Input Note: SRXD Input in Synchronous mode only Figure 44. SSI Transmitter External Clock Timing Diagram CK Input FS (bl) Input FS (wl) Input SRXD Input Figure 45. SSI Receiver External Clock Timing Diagram MC9328MX21 Technical Data, Rev. 3 Freescale Semiconductor ...

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... CK high to STXD high 27b (Tx) CK high to STXD low 28 (Tx) CK high to STXD high impedance 29 SRXD setup time before (Rx) CK low 30 SRXD hole time after (Rx) CK low Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 1 Internal Clock Operation (SAP Ports) 91 -3.30 -3.93 -3 ...

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... Freescale Semiconductor Unit Unit ...

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... CK high to FS (bl) low 6 (Tx) CK high to FS (wl) high 7 (Rx) CK high to FS (wl) high 8 (Tx) CK high to FS (wl) low 9 (Rx) CK high to FS (wl) low 10 (Tx) CK high to STXD valid from high impedance Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 10.22 10.79 10.22 10.79 10.22 10.79 10.05 10 ...

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... Freescale Semiconductor Unit ...

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... CK high to FS (wl) high 24 (Tx) CK high to FS (wl) low 25 (Rx) CK high to FS (wl) low 26 (Tx) CK high to STXD valid from high impedance 27a (Tx) CK high to STXD high 27b (Tx) CK high to STXD low Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 1 Internal Clock Operation (SSI3 Ports) 91 -2.09 -2.74 -2.09 -2 ...

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... MC9328MX21 Technical Data, Rev. 3.4 3.0 V ± 0.3 V Maximum Minimum Maximum 16.46 7.29 14.97 – 1.49 – – 0 – – 21.99 – – 0 – – 3.80 – – 0 – AutoClear RPP Control Bit DS2502 Tx 60-240us 512us One-Wire samples (set PST) Freescale Semiconductor Unit ...

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... For the Write 1 or Read, the control register WR1/RD is set and auto-cleared when the sequence has been completed. After a Read, the control register RDST bit is set to the value of the read. Freescale Semiconductor AutoClear WR0 Set WR0 ...

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... Table 39. System Clock Requirements NOTE MC9328MX21 Technical Data, Rev. 3.4 Auto Clear WR1/RD Read “1” Slot 117us One-Wire samples (set RDST) 13us Absolute Relative Precision Precision 31 0.0645 7 0.1 32 0.0645 20 0.2 4 0.8 2 0.15 16.8 19. 0.9882 1.023 0.0117 0.023 Freescale Semiconductor ...

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... USBD_TXDP high to USBD_OE deactivated TXDP_ OEB USBD_TXDM low to USBD_OE deactivated (includes SE0) TXDM_ OEB SE0 interval of EOP FEOPT Data transfer rate PERIOD Freescale Semiconductor 6 t PERIOD 2 Parameter MC9328MX21 Technical Data, Rev. 3.4 Specifications t 4 TXDM_OEB 3 t TXDP_OEB t FEOPT 5 3.0 V ± 0.3 V ...

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... LOW period of the SCL clock 6 Setup time for STOP condition 62 Parameter Parameter MC9328MX21 Technical Data, Rev. 3 FEOPR 3.0 V ± 0.3 V Minimum Maximum 82 – 1.8 V ± 0.1 V Minimum Maximum 188 – 0 188 88 – 500 – 500 – 185 – Freescale Semiconductor Unit ns Unit ...

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... Address Chip-select Read (Write) OE (rising edge) OE (falling edge) EB (rising edge) EB (falling edge) LBA (negated falling edge) LBA (negated rising edge) Burst Clock (rising edge) Burst Clock (falling edge) Read Data Write Data (negated falling) Write Data (negated rising) DTACK Freescale Semiconductor ...

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... Freescale Semiconductor Unit ...

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... Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[0] htrans hwrite haddr hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Address CS[0] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Freescale Semiconductor Seq/Nonseq Read V1 Last Valid Data Read Figure 54. WSC = 1, A.HALF/E.HALF MC9328MX21 Technical Data, Rev. 3.4 Specifications ...

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... Last Valid Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Address CS[0] R/W LBA OE EB D[31:0] Figure 55. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF 66 V1 Write Data (V1) Last Valid Data Last Valid Data MC9328MX21 Technical Data, Rev. 3.4 Unknown V1 Write Write Data (V1) Freescale Semiconductor ...

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... V1 hready weim_hrdata Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[0] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 56. WSC = 1, OEA = 1, A.WORD/E.HALF Freescale Semiconductor Address V1 Read 1/2 Half Word MC9328MX21 Technical Data, Rev. 3.4 Specifications V1 Word Address 2/2 Half Word 67 ...

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... Last Valid Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[0] R/W LBA OE EB D[31:0] Figure 57. WSC = 1, WEA = 1, WEN = 1, A.WORD/E.HALF 68 Write Data (V1 Word) Last Valid Data Address V1 1/2 Half Word MC9328MX21 Technical Data, Rev. 3.4 Address Write 2/2 Half Word Freescale Semiconductor ...

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... V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 58. WSC = 3, OEA = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC9328MX21 Technical Data, Rev. 3.4 Specifications V1 Word Address 2/2 Half Word 69 ...

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... BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE EB D[31:0] Last Valid Data Figure 59. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF 70 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX21 Technical Data, Rev. 3.4 Address 2/2 Half Word Freescale Semiconductor ...

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... V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 60. WSC = 3, OEA = 4, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC9328MX21 Technical Data, Rev. 3.4 Specifications V1 Word Address 2/2 Half Word 71 ...

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... BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 61. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF 72 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX21 Technical Data, Rev. 3.4 Address 2/2 Half Word Freescale Semiconductor ...

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... V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 62. WSC = 3, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC9328MX21 Technical Data, Rev. 3.4 Specifications V1 Word Address 2/2 Half Word 73 ...

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... V1 hready weim_hrdata weim_hready BCLK Last Valid Addr A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 63. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF 74 Last Valid Data Address V1 Read 1/2 Half Word MC9328MX21 Technical Data, Rev. 3.4 V1 Word Address 2/2 Half Word Freescale Semiconductor ...

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... A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 64. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX21 Technical Data, Rev. 3.4 Specifications Unknown Address 2/2 Half Word ...

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... A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 65. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF 76 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX21 Technical Data, Rev. 3.4 Unknown Address 2/2 Half Word Freescale Semiconductor ...

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... BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 66. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF Freescale Semiconductor Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX21 Technical Data, Rev. 3.4 Specifications Write Data ...

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... EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 67. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF 78 Read Idle Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX21 Technical Data, Rev. 3.4 Write Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Last Valid Addr CS[3:0] R/W LBA OE EB D[31:0] Last Valid Data Figure 68. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF Freescale Semiconductor Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC9328MX21 Technical Data, Rev. 3.4 Specifications Address Write Data (2/2 Half Word) ...

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... R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 69. WSC = 3, CSA = 1, A.HALF/E.HALF 80 Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX21 Technical Data, Rev. 3.4 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 70. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF Freescale Semiconductor Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC9328MX21 Technical Data, Rev. 3.4 Specifications Read Data (V2) ...

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... OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 71. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF 82 Idle Nonseq Write V8 Last Valid Data Address V1 CNC Read Read Data Last Valid Data MC9328MX21 Technical Data, Rev. 3.4 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 72. WSC = 3, SYNC = 1, A.HALF/E.HALF Freescale Semiconductor Nonseq Read V5 Address V1 Read V1 Word V2 Word MC9328MX21 Technical Data, Rev. 3.4 Specifications Idle Address V5 V5 Word V6 Word 83 ...

Page 84

... Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 73. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD 84 Seq Seq Read Read Word V2 Word Address V1 Read V1 Word V2 Word MC9328MX21 Technical Data, Rev. 3.4 Idle Seq Read V4 V3 Word V4 Word V3 Word V4 Word Freescale Semiconductor ...

Page 85

... Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 74. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF Freescale Semiconductor Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC9328MX21 Technical Data, Rev. 3.4 Specifications Idle V2 Word Address V2 ...

Page 86

... Last Valid A[24:0] Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 75. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF 86 Last Valid Data Address V1 Read V1 1/2 MC9328MX21 Technical Data, Rev. 3.4 Idle Seq Read V2 V1 Word V2 Word V1 2/2 V2 1/2 V2 2/2 Freescale Semiconductor ...

Page 87

... BCLK Last Valid A[24:0] Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 76. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read V1 1/2 MC9328MX21 Technical Data, Rev. 3.4 Specifications Idle Seq Read V2 V1 Word V2 Word ...

Page 88

... Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The waveforms in the following section provide examples of the DTACK signal operation. 88 Specifications” for more information on how to generate MC9328MX21 Technical Data, Rev. 3.4 Freescale Semiconductor ...

Page 89

... DTACK Example Waveforms: Internal ARM AHB Word Accesses to Word-Width (32-bit) Memory HCLK BCLK Last Valid ADDR Addr CS[5] RW LBA OE EB (EBC=0) EB (EBC=1) DTACK DATA_IN Figure 77. DTACK Edge Triggered Read Access, WSC=3F, OEA=8, OEN=5, AGE=1. Freescale Semiconductor V1 Read MC9328MX21 Technical Data, Rev. 3.4 Specifications V1 Data 89 ...

Page 90

... Last Valid Addr CS[0] RW LBA OE EB (EBC=0) EB (EBC=1) DTACK DATA_IN Figure 78. DTACK Level Sensitive Sequential Read Accesses, WSC=2, EW=1, DCT=1, AGE=0 (Example of 90 Address V1 Read DCT V1 Word DTACK Remaining High) MC9328MX21 Technical Data, Rev. 3.4 V1+8 V1+4 V1+4 Word V1+8 Word Freescale Semiconductor ...

Page 91

... BCLK ADDR Last Valid Addr CS[0] RW LBA OE EB DTACK DATA_OUT Figure 79. DTACK Level Sensitive Sequential Write Accesses, WSC=2, EW=1, RWA=1, RWN=1, DCT=1, Freescale Semiconductor Address V1 RWA RWN Write DCT V1 Word AGE=0 (Example of DTACK Asserting) MC9328MX21 Technical Data, Rev. 3.4 Specifications V1+4 ...

Page 92

... MC9328MX21 Technical Data, Rev. 3 3.0 V ± 0.3 V Minimum Maximum 100 0 100 – 111.1 – 69.7 0 72.3 – 1.76 – – 68.3 – – 335.1 – – 111.1 – Figure 82 shows the timing diagram Table 45. The formula for Freescale Semiconductor Unit kHz ...

Page 93

... Table 45. Gated Clock Mode Timing Parameters Number 1 csi_vsync to csi_hsync 2 csi_hsync to csi_pixclk 3 csi_d setup time 4 csi_d hold time 5 csi_pixclk high time 6 csi_pixclk low time 7 csi_pixclk frequency HCLK = AHB System Clock, T HCLK Freescale Semiconductor 1 2 Valid Data Valid Data Valid Data Valid Data 3 4 Parameter Minimum HCLK 3 ...

Page 94

... Figure 83. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge 94 Figure 84 Section 3.22.3, “Calculation of Pixel Clock Rise/ 1 Valid Data Valid Data 2 3 MC9328MX21 Technical Data, Rev. 3.4 shows the timing diagram Table 46. The formula for Valid Data Freescale Semiconductor ...

Page 95

... Falling-edge latch data • max fall time allowed = (negative duty cycle - hold time) • max rise time allowed = (positive duty cycle - setup time) Freescale Semiconductor 1 Valid Data Valid Data 2 3 Parameter ...

Page 96

Pin Assignment and Package Information OE_ LD9 LD12 LD14 REV HSYNC SD2_D2 A ACD CON LD7 LD5 LD11 LD16 PS SD2_D0 B TRAST LD1 LD3 LD6 LD10 LD17 VSYNC SD2_D3 C LD2 LD0 ...

Page 97

... MAPBGA Package Dimensions Figure 85 illustrates the MAPBGA 14 mm × × 1.41 mm package, which has 0.65 mm ball pitch. Figure 85. i.MX21 MAPBGA Mechanical Drawing Freescale Semiconductor MC9328MX21 Technical Data, Rev. 3.4 Pin Assignment and Package Information 97 ...

Page 98

... Pin Assignment and Package Information 4.2 MAPBGA Package Dimensions Figure 86 illustrates the MAPBGA 17 mm × × 1.45 mm package, which has 0.8 mm spacing between the pads. Figure 86. i.MX21 MAPBGA Mechanical Drawing 98 MC9328MX21 Technical Data, Rev. 3.4 Freescale Semiconductor ...

Page 99

... Updated the table by removing the table footnote Table 1 on page 3 Added VM and CVM devices. Table 7 on page 16 Updated Sleep Current values. Table 1 on page 4 Added a part number MC9328MX21CJM and a footnote. Freescale Semiconductor Table 48. Document Revision History Description of Change MC9328MX21 Technical Data, Rev. 3.4 Document Revision History 99 ...

Page 100

... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase ...