MPC8349EVVAJFB Freescale, MPC8349EVVAJFB Datasheet - Page 29

• Manufacturer Part Number: MPC8349EVVAJFB
• Manufacturer: Freescale

Specifications of MPC8349EVVAJFB

• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 533MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: TBGA
• Lead Free Status / RoHS Status: Compliant

8.2.3.2
Table 30
Figure 14
Freescale Semiconductor
At recommended operating conditions with LV
PMA_RX_CLK clock period
PMA_RX_CLK skew
RX_CLK duty cycle
RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising
PMA_RX_CLK
RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising
PMA_RX_CLK
RX_CLK clock rise time (20%–80%)
RX_CLK clock fall time (80%–20%)
Notes:
1. The symbols for timing specifications follow the pattern of t
2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times
and t
(TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
is based on three letters representing the clock of a particular function. For example, the subscript of t
(T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For
symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX).
of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0.
(first two letters of functional block)(reference)(state)(signal)(state)
provides the TBI receive AC timing specifications.
shows the TBI receive AC timing diagram.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
TBI Receive AC Timing Specifications
PMA_RX_CLK1
PMA_RX_CLK0
Parameter/Condition
RCG[9:0]
Table 30. TBI Receive AC Timing Specifications
TRX
Figure 14. TBI Receive AC Timing Diagram
DD
TRDXKH
clock reference (K) going to the high (H) state. In general, the clock reference symbol
t
t
SKTRX
TRXH
/OV
t
TRDVKH
DD
symbolizes TBI receive timing (TR) with respect to the time data input signals
of 3.3 V ± 10%.
t
TRX
t
TRXH
Even RCG
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
t
Symbol
TRXH
t
t
TRDXKH
TRDVKH
t
SKTRX
t
t
t
TRXR
TRXF
t
TRX
TRXF
/t
TRX
1
2
2
Odd RCG
t
TRDXKH
Ethernet: Three-Speed Ethernet, MII Management
t
Min
TRXR
7.5
2.5
1.5
0.7
0.7
40
t
TRDVKH
TRDVKH
t
TRDXKH
TRX
16.0
Typ
symbolizes TBI receive timing
—
—
—
—
—
—
clock reference (K) going to
TRX
represents the TBI
Max
8.5
2.4
2.4
60
—
—
for inputs
Unit
ns
ns
ns
ns
ns
ns
%
29