TLE7230G-L Infineon Technologies, TLE7230G-L Datasheet - Page 9

• Manufacturer Part Number: TLE7230G-L
• Manufacturer: Infineon Technologies

Specifications of TLE7230G-L

• Switch Type: Low Side
• Power Switch Family: TLE7230G
• Input Voltage: -0.3 to 6V
• Power Switch On Resistance: 800mOhm
• Output Current: 1A
• Number Of Outputs: 8
• Mounting: Surface Mount
• Supply Current: 1mA
• Package Type: DSO
• Operating Temperature (min): -40C
• Operating Temperature (max): 150C
• Operating Temperature Classification: Automotive
• Pin Count: 24
• Lead Free Status / RoHS Status: Compliant

SO – Signal Output of the Serial Peripheral Interface
SI – Signal Input of the Serial Peripheral Interface. The pin has an internal pull down structure.
SCLK – Clock Input of the Serial Peripheral Interface. The pin has an internal pull down structure
SPI
The SPI is a Serial Peripheral Interface with 4 digital pins
and an 16 bit shift register. The SPI is used to configure and
program the device, turn on and off channels and to read
detailed diagnostic information.
SPI Signal Description:
CS - Chip Select. The system microcontroller selects the TLE 7230 R/G by means of the CS pin.
Whenever the pin is in a logic low state, data can be transferred from the µC and vice versa.
•
CS = L : SPI is working like a shift register. With each clock signal at the SCLK pin the state of the SI is
read into the SPI shift-register (falling clock edge) and one diagnosis bit is written out of SO (rising ris-
ing edge).
CS = L H:
•
•
To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low
transition of CS. The SPI of the TLE7230G/R has a modulo 8 counter integrated. If the number of
clock signals is not an integer multiple of 8 the SPI will not accept the data in the shift register and the
fault register will not be reset.
SCLK - Serial Clock. The serial clock pin clocks the internal SPI shift register of the TLE7230G/R. The
serial input (SI) accepts data into the input SPI shift register on the falling edge if while the serial output
(SO) shifts diagnostic information out of the SPI shift register on the rising edge of serial clock. It is es-
sential that the SCLK pin is in a logic low state whenever chip select CS makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit (MSB) first. SI infor-
mation is read in on the falling edge . Input data is latched in the SPI shift register and then transferred
to the internal registers of the logic.
V1.1
Serial input
data MSB first
SI
SO changes from high impedance state to logic high or low state corresponding to the SO bits
transfer of SI bits from SPI shift register into the internal logic registers
reset of diagnosis register if sent command was valid
LSB
LSB
internal logic registers
16 bit SPI shift register
CS
diagnosis register
CS
T a r g e t D a t a s h e e t T L E 7 2 3 0 R / G
MSB
MSB
Serial output
(diagnosis)
MSB first
Page
SO
9
CS = H : Any signals at the SCLK and SI
pins are ignored and SO is forced into a
high impedance state.
CS = H L :
•
•
diagnostic information is transferred
from the diagnosis register into the SPI
shift register. (in sleep mode no tranfer
of diagnostic information)
serial input data can be clocked into the
SPI shift register from then on
SCLK
SO
CS
SI
SPI
12. Oct. 2003