LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 89

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Features
6
6.1
Table 6-1.
6.2
Datasheet
Features
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for configuration purposes, the processor does not distinguish between
a "warm" reset and a "power-on" reset.
Power-On Configuration Option Signals
Note:
1.
2.
3.
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See
power states.
Output tristate
Execute BIST
Disable dynamic bus parking
Symmetric agent arbitration ID
RESERVED
Asserting this signal during RESET# will select the corresponding option.
Address signals not identified in this table as configuration options should not be asserted during RESET#.
Disabling of any of the cores within the processors must be handled by configuring the EXT_CONFIG Model
Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the package.
Configuration Option
Figure 6-1
for a visual representation of the processor low
A[24:4]#, A[35:26]#
Table
Signal
BR0#
SMI#
A25#
A3#
6-1.
1,2
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