LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 14

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

2.2.3
2.3
14
FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation. Decoupling
guidelines are described in the appropriate platform design guidelines.
Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage
to be delivered to the processor VCC lands (see
specifications). Refer to
for each processor frequency is provided in
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in
Specification Update for further details on specific valid core frequency and VID values
of the processor. Note that this differs from the VID employed by the processor during
a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep
technology, or Extended HALT State).
The processor uses
selection of power supply voltages. Table 2-1 specifies the voltage level corresponding
to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers
to a low voltage level. If the processor socket is empty
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself. The Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket defines VID [7:0], VID7 and VID0 are not
outputs of the processor but are strapped to V
VID7 must be connected to the VR controller for compatibility with future processors.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (V
line. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted.
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 2-4
The VRM or VRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in
and
Table
and
2-4. Refer to the Voltage Regulator Design Guide for further details.
Figure 2-1
eight
Table 2-11
as measured across the VCC_SENSE and VSS_SENSE lands.
voltage identification signals, VID[7:0], to support automatic
for the DC specifications for these signals. Voltages
CC
). This will represent a DC shift in the load
Table
SS
Table
Chapter 2.6.3
on the processor package. VID0 and
2-3.
2-3. Refer to the Processor
Table 2-3
(VID[7:0] =
for V
includes VID step sizes
Electrical Specifications
CC
11111110), or the
overshoot
®
Table 2-3
Datasheet