HS1-82C55ARH-8 Intersil, HS1-82C55ARH-8 Datasheet - Page 14

• Manufacturer Part Number: HS1-82C55ARH-8
• Manufacturer: Intersil

Specifications of HS1-82C55ARH-8

• Operating Temperature (max): 125C
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Compliant

Operating Modes
MODE 2 (Strobed Bidirectional Bus I/O)
The functional configuration provides a means for
communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O). “Handshaking” signals are provided
to maintain proper bus flow discipline similar to MODE 1.
Interrupt generation and enable/disable functions are also
available.
Mode 2 Basic Functional Definitions:
Bidirectional Bus I/O Control Signal Definition
INTR (INTERRUPT REQUEST)
A high on this output can be used to interrupt the CPU for
both input or output operations. INTR will be set either by the
rising edge of ACK (INTE1 = 1) or the rising edge of STB
(INTE2 = 1). INTR will be reset by the falling edge of WR (if
previously set by the rising edge or ACK), the falling edge of
RD (if previously set by the rising edge of STB), or the falling
edge of WR when immediately following a low RD pulse or
the falling edge of RD when immediately following a low WR
pulse (if previously set by the rising edges of both ACK and
STB).
Output Operations
OBF (OUTPUT BUFFER FULL)
The OBF output will go “low” to indicate that the CPU has
written data out to Port A.
ACK (ACKNOWLEDGE)
A “low” on this input enables the three-state output buffer of
Port A to send out the data. Otherwise, the output buffer will
be in the high impedance state.
INTE 1 (THE INTE FLIP-FLOP ASSOCIATED WITH OBF)
Controlled by Bit Set/Reset of PC6.
Input Operations
STB (STROBE INPUT)
A “low” on this input loads data into the input latch.
IBF (INPUT BUFFER FULL F/F)
A “high” on this output indicates that data has been loaded
into the input latch.
INTE 2 (THE INTE FLIP-FLOP ASSOCIATED WITH IBF)
Controlled by Bit Set/Reset of PC4.
• Used in Group A only.
• One 8-bit, bidirectional bus port (Port A) and a 5-bit
• Both inputs and outputs are latched.
• The 5-bit control port (Port C) is used for control and
control port (Port C).
status for the 8-bit, bidirectional bus port (Port A).
14
HS-82C55ARH
NOTE: Any sequence where WR occurs before ACK and STB
occurs before RD is permissible.
PERIPHERAL
D7 D6 D5 D4 D3 D2 D1 D0
1
INTR
OBF
ACK
BUS
STB
WR
RD
WR
IBF
RD
DATA FROM PERI-
PHERAL TO
HS-82C55ARH
0
FIGURE 21. MODE 2 (BIDIRECTIONAL)
FIGURE 22. MODE 2 (BIDIRECTIONAL)
CONTROL WORD
FIGURE 20. MODE CONTROL WORD
TWHOL
TSLIH
1/0 1/0 1/0
DATA FROM CPU
TO HS-82C55ARH
TSHPX
INTE
INTE
TPVSH
TKLPV
1
2
TSLSH
PC2- PC0
DATA FROM
HS-82C55ARH
TO PERIPHERAL
PA7- PA0
TKHOL
PC3
PC7
PC6
PC7
PC6
PC2 - PC0
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
GROUP B MODE
0 = MODE 0
1 = MODE 1
3
TKLKH
8
INTR A
OBF A
ACK A
STB A
IBF A
I/O
TRHIL
DATA FROM
HS-82C55ARH
TO CPU
TKHPX