HS1-82C55ARH-8 Intersil, HS1-82C55ARH-8 Datasheet - Page 12

• Manufacturer Part Number: HS1-82C55ARH-8
• Manufacturer: Intersil

Specifications of HS1-82C55ARH-8

• Operating Temperature (max): 125C
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Compliant

Mode 0 Configurations
Operating Modes
Mode 1 (Strobed Input/Output)
This functional configuration provides a means for
transferring I/O data to or from a specified port in conjunction
with strobes or “handshaking” signals. In Mode 1, Port A and
Port B use the lines on Port C to generate or accept these
“handshaking” signals.
Mode 1 Basic Functional Definitions:
Input Control Signal Definition
STB (Strobe Input)
A “low” on this input loads data into the input latch.
IBF (Input Buffer Full F/F)
A “high” on this output indicates that the data has been
loaded into the input latch; in essence, an acknowledgment.
IBF is set by STB input being low and is reset by the rising
edge of the RD input.
D7 - D0
D7 - D0
• Two Groups (Group A and Group B)
• Each group contains one 8-bit port and one 4-bit
• The 8-bit data port can be either input or output. Both
• The 4-bit port is used for control and status of the 8-bit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
1
control/data port.
inputs and outputs are latched.
port.
0
0
0
0
1
1
1
1
CONTROL WORD #12
CONTROL WORD #14
0
0
0
1
0
0
12
A
C
B
A
C
B
(Continued)
8
4
4
8
8
4
4
8
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
HS-82C55ARH
INTR (Interrupt Request)
A “high” on this output can be used to interrupt the CPU
when an input device is requesting service. INTR is set by
the rising edge of STB and reset by the falling edge of RD.
This procedure allows an input device to request service
from the CPU by simply strobing its data into the port.
INTE A
Controlled by Bit Set/Reset of PC4.
INTE B
Controlled by Bit Set/Reset of PC2.
RD
D7 D6 D5 D4 D3 D2 D1 D0
PC6, 7
1 = INPUT
0 = OUTPUT
1
D7 - D0
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
MODE 1 (PORT A)
CONTROL WORD
0
0
INTE
1
A
PA7 - PA0
0
0
1 1/0
PC6, 7
1
1
PC4
PC5
PC3
1
1
FIGURE 15. MODE 1 INPUT
CONTROL WORD #13
CONTROL WORD #15
2
0
0
8
0
1
I/O
STB
A
IBF
A
INTR
A
1
1
A
C
B
A
C
B
RD
D7 D6 D5 D4 D3 D2 D1 D0
1
MODE 1 (PORT B)
CONTROL WORD
INTE
B
PB7 - PB0
8
4
4
8
8
4
4
8
PC2
PC1
PC0
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
1
8
1
STB
B
IBF
B
INTR
B