NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 16

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

Errata
23.
Problem:
Implication:
Workaround:
Status:
24.
Problem:
Implication:
Workaround:
Status:
25.
Problem:
Implication:
16
Configuration transaction may be ignored in MCH when Configuration
Request Retry Status is enabled in PCI Express to PCI/PCI-X bridges
Under certain circumstances that include a mix of PCI Express traffic in the presence of
completions with Configuration Retry Status (configuration space traffic receiving CRS, and other
traffic that is posted / governed by Posted Flow Control credits) on a given PCI Express port, the
MCH may ignore and fail to issue an outbound configuration space access indefinitely. This
behavior has been observed in configurations with PCI Express to PCI/PCI-X bridge devices under
circumstances where at least one device “behind” the bridge is active and operational, while at least
one other device “behind” the bridge remains unresponsive to configuration requests for an
extended period of time. Such failures ultimately manifest themselves as CPU IERR# assertions,
which commonly precipitates a platform reboot. Completions with Configuration Request Retry
Status are generally sent by a PCI Express to PCI/PCI-X bridge when it relays configuration space
traffic to a PCI/PCI-X device which exhibits a long latency in responding to configuration space
traffic. The CRS completion status mechanism is intended to prevent a PCI Express completion
timeout from occurring in cases where historical PCI/PCI-X implementations would experience an
extended latency without response, but would not generate any timeout or associated error.
A system hang may occur.
To avoid configuration transactions from being ignored, Intel strongly recommends that BIOS
should disable Configuration Request Retries in all PCI Express bridge devices. For Intel®
6700PXH 64-bit PCI Hub this is accomplished by clearing the Bridge Configuration Retry Enable
bit in the Device Control register (D0:F0,2:R04Ch bit 15). This bit is cleared by default. Some PCI
or PCI-X devices may require lengthy self-initialization sequence (up to 1.5 sec as defined by PCI
Express Base Specification 1.0a) to complete before they are able to service Configuration
Requests after reset. In order to ensure the ability of the system to successfully enumerate PCI
devices, BIOS should disable PCI Express Completion Timeout in the root port configuration of
MCH links connected to Intel® 6700PXH 64-bit PCI Hub, Intel® IOP332, and Intel® 41210
devices (including add-in cards) by setting the Completion Timeout Timer Disable bit in the
Vendor Specific command register (D2-7:F0:R045h bit 3). BIOS should ensure that the
Completion Timeout Timer remains enabled (default) for other active PCI Express links. BIOS
should also ensure that the Completion Timeout Error Mask is set in MCH root ports associated
with inactive PCI Express links (unpopulated slots or disabled devices) -- refer to erratum 19 for
detail.
For the steppings effected, see the Summary Table of Changes.
PCI Express Hot-Plug indicator blink causes extra SMBus write
When both PCI Express device 4 and 6 are configured for Hot-Plug functionality, an attention or
power indicator blink command sent to the I/O Expander on device 4 will cause an extra SMBus
write to the external I/O expander connected to device 4 and 6. An attention or power indicator
blink command on device 6 will not generate extra SMbus write command for device 4. No failures
have been observed from this erratum.
Extra writes may be observed on the SMbus that have no side effects.
None
For the steppings effected, see the Summary Table of Changes.
PCI Express x4, x8 links may train down to lower width
It has been observed that x4, x8 links may fail to train to their full link widths. This behavior occurs
infrequently. The issue is caused by the MCH exiting the Polling.Active state and entering the
Polling.Config state prior to the downstream device entering the Polling.Active state.
PCI Express ports may fail train to at full width.
Intel
®
E7520 Memory Controller Hub (MCH) Specification Update