NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 13

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

Workaround:
Status:
14.
Problem:
Implication:
Workaround:
Status:
15.
Problem:
Implication:
Workaround:
Status:
16.
Problem:
Implication:
Workaround:
Status:
Intel
®
E7520 Memory Controller Hub (MCH) Specification Update
Upon initial training and after each retrain or secondary bus reset, clear the correctable error
detected bit of the PCI Express Device Status register (EXP_DEVSTS, Device 2-7, Function 0,
Offset 6E-6Fh bit 0, 1b) and the receiver error status bit of the PCI Express Correctable Error
Status register (EXP_CORERRSTS, Device 2-7, Function 0, Offset 110-113h bit 0, 1b). Also clear
the FERR/NERR bits that flag correctable errors (EXP_FERR/EXP_NERR, Device 2-7, Function
0, Offset 160-163h / 164-167h bit 6, 1b).
For the steppings effected, see the Summary Table of Changes.
DDR2 write offset issue
DQ/DQS signals terminate to a level about 300mv below VDDQ/2 between write bursts. No
functional failures have been observed as a function of this issue.
Signal integrity issues may be observed.
None
For the steppings effected, see the Summary Table of Changes.
DMA MSI interrupt issue
If the MSI enable bit is cleared (disabled) in the MSI Control Register (MSICR - Device 1,
Function 0, Offset B0-B3h bit 16, 0b) while DMA channels are active and generating interrupts,
then corrupted MSI interrupts may be generated.
The MSI interrupt handler should not clear the MSI enable bit when DMA channels are in an active
state or the system may hang due to the corrupted MSI.
The following algorithm can be used to service MSI without having to disable them:
For the steppings effected, see the Summary Table of Changes.
SEC and DED error counters aliased in mirror mode
During a read from DRAM in memory mirroring mode, the destination of the read (primary or
mirrored DIMM) is dependent upon SA15, the state of the DDRCSR FSM Mirror State Transition
Qualifier (Device 0, Function 0, Offset 9A-9Bh bits 11:10) and whether the access is a first or
second attempt due to DED retry. If a correctable or uncorrectable error is encountered during a
read, the primary DIMM’s SEC or DED counter increments regardless of whether the primary or
mirror DIMM was accessed. The mirror DIMM’s counters do not increment in mirror mode.
In mirroring mode, primary DIMM SEC and DED error counters reflect the total number of errors
across both the primary and mirror DIMMs.
Refer to the E7520, E7320 and E7525 BIOS Specification Update for workaround details.
For the steppings effected, see the Summary Table of Changes.
1. Check for MSI interrupt status. Check the DMA Controller Global Status Register (Device 1,
2. Clear interrupt status in the Channel Status Registers for the respective channels.
3. Handle pending interrupts.
4. Exit if no interrupt status is set, else loop back to step 2 and repeat
Function 0, BAR 10h, Offset 104-107h bits 0-1, 8-9, 16-17, 24-25) to isolate the DMA channel
generating the interrupt and then check the appropriate Channel Status Register for additional
information about the interrupt (Device 1, Function 0, BAR 10h, Offsets 1C-1Fh, 44-47h, 80-
83h & C4-C7).
Once the handler has verified a read with no status set, it is safe to return, because any
subsequent interrupt event will generate a new MSI, so the routine will need to be called again
after it exits.
Errata
13