NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 11

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

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Intel
®
E7520 Memory Controller Hub (MCH) Specification Update
PCI Express* add-in card presence detect state misreported
PCI Express ports that are configured as non-hot plug capable incorrectly assert the add-in card
Presence Detect State in the PCI Express Slot Status Register (EXP_SLTSTS Device 2-7, Function
0, Offset 7E-7Fh bit 6) regardless of the presence of an add-in card.
Software may interpret the presence of an add-in card when none exists.
Utilize the Link Active bit in the Vendor Specific Status Register 1(VS_STS1 Device 2-7, Function
0, Offset 47h bit 1) as an alternative to the Presence Detect State bit.
For the steppings effected, see the Summary Table of Changes.
Incorrect PCI Express Link/Lane numbers driven in degraded link
If a failure of receiver detect or bit/symbol lock occurs on lane 0 (lane 7 in the case of physical lane
reversal) while other lanes successfully achieve bit/symbol lock in the early stages of
Polling.Active, the MCH will exhibit anomalous lane numbering during the ensuing failed training
sequence. Note that this anomalous behavior only occurs in situations where the combination of
successful and failing lanes will result in a training failure, and a return to the Polling state.
When such a failed training is in progress, non-compliant non-PAD lane numbers may be observed
on the MCH downstream lanes. The observed behavior may be seen as the MCH attempting a link
split.
None
For the steppings effected, see the Summary Table of Changes.
PCI Express Compliance Mode issue
When a x8 link exits PCI Express Compliance Mode, the MCH will attempt to retrain as two x4
links. This issue manifests itself when the MCH inadvertently enters Compliance Mode.
Upon exiting Compliance Mode, the MCH link will attempt to train a downstream x8 device as two
separate x4 links. Depending on the capabilities of the downstream device, the link width will be
configured as either x4 or x1.
Set bit 0 to 1b in Bus 0, Device 0, Function 0, Offset F5h. This will force the MCH to not enter
compliance mode. Note that the MCH defaults to Compliance Mode disabled.
For the steppings effected, see the Summary Table of Changes.
PCI Express Hot-Plug MSI interrupt issue
During a link down state, the MCH will not send MSI interrupts to the front side bus. In general
MSI messages need not be delivered when the link is down, but in the event that MSI interrupt
routing is used on Hot-Plug events, the processor will wait indefinitely for this interrupt. Waiting
for command complete interrupts is a normal part of the steps in the orderly removal process, and
link down will occur at the point that power is removed from the slot. Subsequent accesses to the
slot control register to update indicators and power control will not generate the expected MSI
interrupts from the MCH until slot power is restored, and the link is back up.
Hot-Plug software written to wait for command complete interrupts will hang in MSI interrupt
mode.
Run in either of the other two interrupt modes (the “legacy” method using the MCHGPE# to signal
hot-plug interrupts to the ICH or “native” interrupt mode using PCI interrupts (INTA#)).
Alternatively in MSI mode, software may poll for command complete rather than wait for MSI, or
implement the command complete timeout to continue to the next slot control update rather than
repeat the current slot control update.
For the steppings effected, see the Summary Table of Changes.
Errata
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