NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 10

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

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10
DMA channel source address checking error
In the DMA controller memory mapped registers, bit 6 of the DCRs (Descriptor Control Registers
Memory Mapped I/O Address Offset 2Ch-2Fh, 6Ch-6Fh, 0ACh-A7h, 0ECh-EFh) for channels 0-3
should be RO, but is implemented as RW.
The DMA controller does not implement error checking for this case if this bit is set to “1”.
Do not write a ‘1’ to bit 6 of the DCRx for channels 0-3.
For the steppings effected, see the Summary Table of Changes.
Data corruption after an illegal front side bus configuration Write
When an illegal FSB configuration write occurs (bits [30:24] of the Configuration Address
Register (CONFIG_ADDRESS, I/O address 0CF8h) are non-zero) PCI configuration accesses
following this write may be corrupted.
This is a mishandled error case and causes corruption of transactions after this transaction. This is
an illegal case.
Do not write non-zero values to the PCI configuration address register reserved fields.
For the steppings effected, see the Summary Table of Changes.
Improper ECC and Memory Initialization while in Symmetric mode
ECC and memory initialization is not properly executed when the MCH is in Symmetric
Addressing mode. The MCH automatically enters symmetric address bit permuting when precisely
four identical ranks of memory are available.
Correctable and uncorrectable memory errors may be detected since ECC is not properly
initialized. The entire memory array is not initialized with zeros.
Refer to your Intel representative for details
For the steppings effected, see the Summary Table of Changes.
Single Channel ECC Error Injection issue
In single channel mode, single ECC error injection to Quad-word 4/5 or Quad-word 6/7 is not
functional. The “Inject all” function works for all Quad-words as expected, as do all injection cases
in dual channel mode.
Injected errors will not propagate to the memory array. As a result, when the memory location is
read, the Correctable Read Memory Error Channel B and Correctable Read Memory Error Channel
A of the DRAM_FERR Register (Device 0, Function 1, Offset 80h bit 0 and 8 Respectively) report
no errors.
Use “inject always” or limit error injection via the ECCDIAG register to the first half of the cache
line when in single channel mode.
For the steppings effected, see the Summary Table of Changes.
Intel
®
E7520 Memory Controller Hub (MCH) Specification Update