JG82845 S L8D8 Intel, JG82845 S L8D8 Datasheet - Page 88

• Manufacturer Part Number: JG82845 S L8D8
• Manufacturer: Intel

Specifications of JG82845 S L8D8

• Lead Free Status / RoHS Status: Compliant

Register Description
3.6.14
3.6.15
88
IOBASE1—I/O Base Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This register controls the hosts to AGP I/O access routing based on the following formula:
Only upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are
treated as 0. Thus, the bottom of the defined I/O address range is aligned to a 4 KB boundary.
IOLIMIT1—I/O Limit Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This register controls the hosts to AGP I/O access routing based on the following formula:
Only upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are
assumed to be FFFh. Thus, the top of the defined I/O address range is at the top of a 4 KB aligned
address block.
IO_BASE
IO_BASE
Bit
7:4
3:0
Bit
7:4
3:0
I/O Address Base. Corresponds to A[15:12] of the I/O address. (Default=F0h)
Reserved.
I/O Address Limit. Corresponds to A[15:12] of the I/O address. (Default=0)
Reserved. (Only 16-bit addressing supported.)
address
address
IO_LIMIT
O_LIMIT
1Ch
F0h
R/W
8 bits
1Dh
00h
R/W
8 bits
Description
Description
Intel
®
82845 MCH for SDR Datasheet
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