JG82845 S L8D8 Intel, JG82845 S L8D8 Datasheet - Page 43

• Manufacturer Part Number: JG82845 S L8D8
• Manufacturer: Intel

Specifications of JG82845 S L8D8

• Lead Free Status / RoHS Status: Compliant

3.5
Intel
Table 8. Intel
®
82845 MCH for SDR Datasheet
R
Host-Hub Interface Bridge Device Registers
(Device 0)
Table 8 provides the register address map for Device 0 PCI configuration space. An “s” in the
Default Value column indicates that a strap determines the power-up default value for that bit.
Address
®
2C–2Dh
2E–2Fh
7C–7Fh
14–2Bh
52–5Fh
68–6Fh
78–7Bh
00–01h
02–03h
04–05h
06–07h
10–13h
30–33h
35–50h
60–67h
70–73h
73–77h
80–85h
Offset
MCH Configuration Space (Device 0)
0Ah
0Bh
0Dh
0Eh
08h
09h
0Fh
34h
51h
86h
DERRSYN
Register
APBASE
CAPPTR
DRB[0:7]
PCICMD
Symbol
PCISTS
AGPM
SUBC
SVID
BCC
HDR
DRA
DRC
MLT
DRT
VID
DID
RID
SID
—
—
—
—
—
—
—
—
—
Aperture Base Configuration
Capabilities Pointer
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Reserved.
Sub-Class Code
Base Class Code
Master Latency Timer
Header Type
Reserved.
Reserved.
Subsystem Vendor Identification
Subsystem Identification
Reserved.
Reserved.
AGP Miscellaneous Configuration
Reserved.
DRAM Row Boundary (8 registers)
Reserved.
DRAM Row Attribute (4 registers)
Reserved.
DRAM Timing Register
DRAM Controller Mode
Reserved.
DRAM Error Syndrome
Register Name
8086h
1A30h
0006h
0090h
03h, 04h
—
00h
06h
00h
00h
—
00000008h
—
0000h
0000h
—
A0h
—
00h
—
00h
—
00h
—
00000010h
0000h
—
00h
Default
Value
Register Description
RO
RO, R/W
RO
RO, R/W
R/WO
R/WO
RO
R/W
R/W
R/W
R/W
R/W, RO
RO
RO, R/WC
—
RO
RO
RO
RO
—
—
—
—
—
—
—
—
RO
Access
43