JG82845 S L8D8 Intel, JG82845 S L8D8 Datasheet - Page 40
JG82845 S L8D8
Manufacturer Part Number
JG82845 S L8D8
Description
Manufacturer
Intel
Datasheet
1.JG82845_S_L8D8.pdf
(148 pages)
Specifications of JG82845 S L8D8
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Register Description
3.4.4
40
CSBSTR—Strength Control Register (SCS# Signal Group)
Memory Address Offset:
Default Value:
Access:
Size:
This register controls the drive strength of the I/O buffers for the SCS# signal group. This group
has two possible loadings depending on the width of SDRAM devices used in each row of memory
(x8 or x16). The proper strength can be independently programmed for each configuration. The
actual strength used for each signal is determined by the DRAMWIDTH Register (offset 2Ch).
6:4
2:0
Bit
7
3
Reserved.
SCS# x16 Strength Control. This field selects the signal drive strength.
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X
Reserved.
SCS# x8 Strength Control. This field selects the signal drive strength.
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X
32h
00h
R/W
8 bits
Descriptions
Intel
®
82845 MCH for SDR Datasheet
R
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