JG82845 S L8D8 Intel, JG82845 S L8D8 Datasheet - Page 48
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JG82845 S L8D8
Manufacturer Part Number
JG82845 S L8D8
Description
Manufacturer
Intel
Datasheet
1.JG82845_S_L8D8.pdf
(148 pages)
Specifications of JG82845 S L8D8
Lead Free Status / RoHS Status
Compliant
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Register Description
3.5.5
3.5.6
3.5.7
48
RID—Revision Identification Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register contains the revision number of the MCH Device 0. These bits are read only and
writes to this register have no effect.
SUBC—Sub-Class Code Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register contains the Sub-Class Code for the MCH Device 0.
BCC—Base Class Code Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register contains the Base Class Code of the MCH Device 0.
Bit
7:0
Bit
7:0
Bit
7:0
Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of bridge of the
MCH.
00h = Host bridge.
Revision Identification Number. This is an 8-bit value that indicates the revision identification
number for the MCH Device 0.
03h = A3 Stepping
04h = B0 Stepping
Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the
MCH.
06h = Bridge device.
08h
See table below
RO
8 bits
0Ah
00h
RO
8 bits
0Bh
06h
RO
8 bits
Description
Description
Description
Intel
®
82845 MCH for SDR Datasheet
R
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