LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 75

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

Bit 6 – MIDI Transmit Busy
Bit 6 MIDI Transmit Busy indicates the send (write) state of the MIDI Data port and Command port (Table 38)
There are no interrupts associated with MIDI transmit (write) data.
Bits[5:0]
RESERVED (Reserved bits cannot be written and return ‘0’ when read).
Command Port
The Command port is used to transfer MPU-401 commands to the Command Controller. The Command port is write-
only (Table 39). See Section “MPU-401 Command controller” below.
Interrupt
The MPU-401 IRQ is asserted (‘1’) when either MIDI receive data or a command acknowledge byte is available tot he
host in the MIDI data register (FIGURE 4). the IRQ is deasserted (‘0’) when the host reads the MIDI Data port.
Note: If, following a host read, data is still available in the 16C550A Receive FIFO, the IRQ will remain asserted (‘1’).
The IRQ is enabled when the ‘Activate’ bit in the MPU-401 configuration registers logical device block is asserted ‘1’.
If the Activate bit is deasserted ‘0’, the MPU-401 IRQ cannot be asserted (see Section “MPU-401 Configuration
Registers”).
The MPU-401 IRQ is not affected by MIDI write data, 16C550A transmit-related functions or Receiver Line Status
interrupts.
The factory default Sound Blaster 16 MPU-401 IRQ is 5.
SMSC DS – LPC47M14X
TYPE
NAME
D7
W
COMMAND REGISTER
STATUS PORT
STATUS PORT
D6
W
D7
D6
0
1
0
1
Table 37 – MIDI Receive Buffer Empty Status Bit
D5
W
Table 38 – MIDI Transmit Busy Status Bit
Table 39 – MPU-401 Command Port
MPU-401 I/O BASE ADDRESS+1
MIDI Read/Command Acknowledge data is
available to the host.
MIDI Read/Command Acknowledge data is
NOT available to the host.
The MPU-401 interface is ready to accept a
data/command byte from the host.
The MPU-401 interface is NOT ready to
accept a data/command byte from the host.
D4
W
Page 75
D3
W
DESCRIPTION
DESCRIPTION
D2
W
D1
W
D0
W
DEFAULT
n/a
Rev. 03/19/2001