LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 161

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

SMSC DS – LPC47M14X
LOGICAL
NUMBER
DEVICE
0x0A
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
Serial Port 1
Serial Port 2
Game Port
LOGICAL
Reserved
Reserved
Reserved
Reserved
DEVICE
Runtime
Register
Parallel
KYBD
Block
FDC
Port
Table 65 – I/O Base Address Configuration Register Description
REGISTER
0x60,0x61
0x60,0x61
0x60,0x61
0x60,0x61
0x60,0x61
0x60,0x61
INDEX
n/a
n/a
n/a
n/a
n/a
the base address is on an 8-
ON 8 BYTE BOUNDARIES
ON 4 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
EPP is only available when
Fixed Base Address: 60,64
on 128-byte boundaries
(all modes supported,
on 1 byte boundaries
(EPP Not supported)
[0x0100:0x0FFC]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
[0x0100:0x0FFF]
[0x0000:0x0F7F]
Not Relocatable
byte boundary)
Page 161
BASE I/O
(NOTE 1)
RANGE
n/a
n/a
n/a
n/a
or
+0 : SRA
+1 : SRB
+2 : DOR
+3 : TSR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
n/a
n/a
+0 : Data/ecpAfifo
+1 : Status
+2 : Control
+400h : cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
+402h : ecr
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
n/a
+0 : Data Register
+4 : Command/Status Reg.
n/a
+00: Game Port Register
+00 : PME Status
.
.
.
+5F : Keyboard Scan Code
(See Table in “Runtime Registers”
section for Full List)
BASE OFFSETS
FIXED
Rev. 03/19/2001