LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 20

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

6
6.1
The address map, shown below in Table 1 shows the addresses of the different blocks of the Super I/O immediately
after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and
configuration register block can be moved via the configuration registers. Some addresses are used to access more
than one register.
6.2
The host processor communicates with the LPC47M14x through a series of read/write registers via the LPC interface.
The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or
DMA transfers. All registers are 8 bits wide.
SMSC DS – LPC47M14X
FUNCTIONAL DESCRIPTION
HOST PROCESSOR INTERFACE (LPC)
SUPER I/O REGISTERS
Note:
Note 1: No Addressable Registers in the Hub Block.
Note 2: Logical Device A is referred to as the Runtime Register block or PME Block and may be
Base+(0-5) and +(7)
Base+(0-7)
Base1+(0-7)
Base2+(0-7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
60, 64
Base + 0
Base + (0-5F)
Base + (0-1)
Base + (0-1)
n/a
Refer to the configuration register descriptions for setting the base address.
used interchangeably throughout this document.
ADDRESS
Table 1 – Super I/O Block Addresses
Runtime Registers
Serial Port Com 1
Serial Port Com 2
ECP+EPP+SPP
BLOCK NAME
Configuration
Parallel Port
Floppy Disk
Game Port
MPU-401
USB Hub
KYBD
ECP
Page 20
SPP
EPP
LOGICAL
DEVICE
C
A
B
0
4
5
3
7
9
NOTES
2
1
Rev. 03/19/2001