FDC37B782-NS Standard Microsystems (SMSC), FDC37B782-NS Datasheet - Page 83

• Manufacturer Part Number: FDC37B782-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B782-NS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
ADDR = 6
ADDR = 7
ADDR = 0
ADDR = 1
DLAB = 1
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is
DLAB = 1
ADDRESS*
REGISTER
empty.
TABLE 37 - REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL
Receive Buffer Register (Read Only)
Transmitter Holding Register (Write
Only)
Interrupt Enable Register
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
Scratch Register (Note 4)
Divisor Latch (LS)
Divisor Latch (MS)
REGISTER NAME
84
REGISTER
SYMBOL
(Note 7)
MCR
MSR
RBR
SCR
DLM
THR
FCR
LCR
LSR
DDL
IER
IIR
Data Bit 0
(Note 1)
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERDAI)
"0" if
Interrupt
Pending
FIFO Enable RCVR FIFO
Word Length
Select Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data Ready
(DR)
Delta Clear
to Send
(DCTS)
Bit 0
Bit 0
Bit 8
BIT 0
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID Bit
Reset
Word Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Overrun Error
(OE)
Delta Data Set
Ready (DDSR)
Bit 1
Bit 1
Bit 9
BIT 1