FDC37B782-NS Standard Microsystems (SMSC), FDC37B782-NS Datasheet - Page 130

• Manufacturer Part Number: FDC37B782-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B782-NS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

(as above). However, as the oscillator cell will
require an initialization time, either RESET must
be held active for sufficient time to allow the
oscillator to stabilize. Program execution will
resume as above.
INTERRUPTS
The FDC37B78x provides the two 8042 interrupts,
the IBF and the Timer/Counter Overflow.
MEMORY CONFIGURATIONS
The FDC37B78x provides 2K of on-chip ROM and
256 bytes of on-chip RAM.
Register Definitions
UD
D7
UD
D6
UD
D5
TABLE 59 - STATUS REGISTER
UD
D4
132
Host I/F Data Register
The Input Data and Output Data registers are
each 8 bits wide. A write to this 8 bit register will
load the Keyboard Data Read Buffer, set the OBF
flag and set the KIRQ output if enabled. A read of
this register will read the data from the Keyboard
Data or Command Write Buffer and clear the IBF
flag.
descriptions for more information.
Host I/F Status Register
The Status register is 8 bits wide.
shows the contents of the Status register.
C/D
D3
Refer to the KIRQ and Status register
UD
D2
IBF
D1
TABLE 59
OBF
D0